| Message ID | 20220830022238.28379-3-milkfafa@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/nuvoton: Add NPCM memory controller driver | expand |
On 30/08/2022 05:22, Marvin Lin wrote: > Add dt-bindings document for Nuvoton NPCM memory controller. > > Signed-off-by: Marvin Lin <milkfafa@gmail.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../edac/nuvoton,npcm-memory-controller.yaml | 54 +++++++++++++++++++ > 1 file changed, 54 insertions(+) > create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > > diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > new file mode 100644 > index 000000000000..d5ef7e7a65f9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# This should be in memory-controllers directory. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton NPCM Memory Controller Device Tree Bindings s/Device Tree Bindings// Best regards, Krzysztof
Hi Krzysztof, > > +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml > > @@ -0,0 +1,54 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > + > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# > > This should be in memory-controllers directory. > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Nuvoton NPCM Memory Controller Device Tree Bindings > > s/Device Tree Bindings// Thanks for the review. Next version will move YAML to memory-controllers directory and remove "Device Tree Bindings". Regards, Marvin
diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml new file mode 100644 index 000000000000..d5ef7e7a65f9 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Memory Controller Device Tree Bindings + +maintainers: + - Marvin Lin <kflin@nuvoton.com> + - Stanley Chu <yschu@nuvoton.com> + +description: | + The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error + correction check). + + The memory controller supports single bit error correction, double bit + error detection (in-line ECC in which a section (1/8th) of the memory + device used to store data is used for ECC storage). + + Note, the bootloader must configure ECC mode for the memory controller. + +properties: + compatible: + enum: + - nuvoton,npcm750-memory-controller + - nuvoton,npcm845-memory-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + ahb { + #address-cells = <1>; + #size-cells = <1>; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0xf0824000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + };