diff mbox series

[v2,2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

Message ID 20220905083125.29426-3-zong.li@sifive.com (mailing list archive)
State New, archived
Headers show
Series Use composable cache instead of L2 cache | expand

Commit Message

Zong Li Sept. 5, 2022, 8:31 a.m. UTC 
From: Greentime Hu <greentime.hu@sifive.com>

Since composable cache may be L3 cache if pL2 cache exists, we should use
its original name composable cache to prevent confusion.

Apart from renaming, we also add the compatible "sifive,ccache0" into ID
table.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
---
 drivers/soc/sifive/Kconfig                    |   6 +-
 drivers/soc/sifive/Makefile                   |   2 +-
 .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
 .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
 4 files changed, 94 insertions(+), 93 deletions(-)
 rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
 rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)

Comments

Conor Dooley Sept. 5, 2022, 6:10 p.m. UTC | #1 
Hey Zong Li,
Couple comments on this patch.

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Since composable cache may be L3 cache if pL2 cache exists, we should use

What is a pL2 cache?

> its original name composable cache to prevent confusion.
> 
> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> table.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  drivers/soc/sifive/Kconfig                    |   6 +-
>  drivers/soc/sifive/Makefile                   |   2 +-
>  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
>  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
>  4 files changed, 94 insertions(+), 93 deletions(-)
>  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)

If you're going to rename the header, you need to update all references to
it too, otherwise the other user (the EDAC) is going to have build issues,
i.e. patch 6 needs to get squashed into this one.


> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c
> similarity index 35%
> rename from drivers/soc/sifive/sifive_l2_cache.c
> rename to drivers/soc/sifive/sifive_ccache.c
> index 59640a1d0b28..1b16a196547f 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c

> -static const struct of_device_id sifive_l2_ids[] = {
> +static const struct of_device_id sifive_ccache_ids[] = {
>         { .compatible = "sifive,fu540-c000-ccache" },
>         { .compatible = "sifive,fu740-c000-ccache" },
> +       { .compatible = "sifive,ccache0" },
>         { /* end of table */ },

For v3, I think you should drop the , from the end of the table while
we are already editing it.
Thanks,
Conor.

>  };
>
Conor Dooley Sept. 5, 2022, 6:46 p.m. UTC | #2 
Noticed a another thing, sorry..

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Since composable cache may be L3 cache if pL2 cache exists, we should use
> its original name composable cache to prevent confusion.
> 
> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> table.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  drivers/soc/sifive/Kconfig                    |   6 +-
>  drivers/soc/sifive/Makefile                   |   2 +-
>  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
>  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
>  4 files changed, 94 insertions(+), 93 deletions(-)
>  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
> 

> -static ssize_t l2_write(struct file *file, const char __user *data,
> +static ssize_t ccache_write(struct file *file, const char __user *data,
>                         size_t count, loff_t *ppos)

You need to fix the alignment here as per checkpatch:
CHECK: Alignment should match open parenthesis
#112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
+static ssize_t ccache_write(struct file *file, const char __user *data,
+                       size_t count, loff_t *ppos)

>  {
>         unsigned int val;
> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
>         if (kstrtouint_from_user(data, count, 0, &val))
>                 return -EINVAL;
>         if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
>         else
>                 return -EINVAL;
>         return count;
>  }
>
Zong Li Sept. 6, 2022, 1:44 a.m. UTC | #3 
<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道：
>
> Noticed a another thing, sorry..
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Greentime Hu <greentime.hu@sifive.com>
> >
> > Since composable cache may be L3 cache if pL2 cache exists, we should use
> > its original name composable cache to prevent confusion.
> >
> > Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> > table.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  drivers/soc/sifive/Kconfig                    |   6 +-
> >  drivers/soc/sifive/Makefile                   |   2 +-
> >  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
> >  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
> >  4 files changed, 94 insertions(+), 93 deletions(-)
> >  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
> >  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
> >
>
> > -static ssize_t l2_write(struct file *file, const char __user *data,
> > +static ssize_t ccache_write(struct file *file, const char __user *data,
> >                         size_t count, loff_t *ppos)
>
> You need to fix the alignment here as per checkpatch:
> CHECK: Alignment should match open parenthesis
> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
> +static ssize_t ccache_write(struct file *file, const char __user *data,
> +                       size_t count, loff_t *ppos)
>

I'm not sure why I don't see that by checkpatch, but it looks that it
is actually misalignment there, I would re-check all indents in
source. Thanks.

> >  {
> >         unsigned int val;
> > @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
> >         if (kstrtouint_from_user(data, count, 0, &val))
> >                 return -EINVAL;
> >         if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> > -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> > +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
> >         else
> >                 return -EINVAL;
> >         return count;
> >  }
> >
Zong Li Sept. 6, 2022, 1:52 a.m. UTC | #4 
<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:46寫道：
>
> Hey Zong Li,
> Couple comments on this patch.
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Greentime Hu <greentime.hu@sifive.com>
> >
> > Since composable cache may be L3 cache if pL2 cache exists, we should use
>
> What is a pL2 cache?

The pL2 is stand for private L2 cache, it is a L2 cache in our system.
Perhaps I should change the pL2 to L2 in the description for more
generic.

>
> > its original name composable cache to prevent confusion.
> >
> > Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> > table.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  drivers/soc/sifive/Kconfig                    |   6 +-
> >  drivers/soc/sifive/Makefile                   |   2 +-
> >  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
> >  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
> >  4 files changed, 94 insertions(+), 93 deletions(-)
> >  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
> >  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
>
> If you're going to rename the header, you need to update all references to
> it too, otherwise the other user (the EDAC) is going to have build issues,
> i.e. patch 6 needs to get squashed into this one.
>

Ok, let me merge these two patches, as you mentioned, we probably
don't want to see the build is broken in git bisect as well.

>
> > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c
> > similarity index 35%
> > rename from drivers/soc/sifive/sifive_l2_cache.c
> > rename to drivers/soc/sifive/sifive_ccache.c
> > index 59640a1d0b28..1b16a196547f 100644
> > --- a/drivers/soc/sifive/sifive_l2_cache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
>
> > -static const struct of_device_id sifive_l2_ids[] = {
> > +static const struct of_device_id sifive_ccache_ids[] = {
> >         { .compatible = "sifive,fu540-c000-ccache" },
> >         { .compatible = "sifive,fu740-c000-ccache" },
> > +       { .compatible = "sifive,ccache0" },
> >         { /* end of table */ },
>
> For v3, I think you should drop the , from the end of the table while
> we are already editing it.

Thanks, I will remove it.

> Thanks,
> Conor.
>
> >  };
> >
>
Conor Dooley Sept. 6, 2022, 6:23 a.m. UTC | #5 
On 06/09/2022 02:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> <Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道：
>>
>> Noticed a another thing, sorry..
>>
>> On 05/09/2022 09:31, Zong Li wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Greentime Hu <greentime.hu@sifive.com>
>>>
>>> Since composable cache may be L3 cache if pL2 cache exists, we should use
>>> its original name composable cache to prevent confusion.
>>>
>>> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
>>> table.
>>>
>>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>>> Signed-off-by: Zong Li <zong.li@sifive.com>
>>> ---
>>>   drivers/soc/sifive/Kconfig                    |   6 +-
>>>   drivers/soc/sifive/Makefile                   |   2 +-
>>>   .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
>>>   .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
>>>   4 files changed, 94 insertions(+), 93 deletions(-)
>>>   rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>>>   rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
>>>
>>
>>> -static ssize_t l2_write(struct file *file, const char __user *data,
>>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>>>                          size_t count, loff_t *ppos)
>>
>> You need to fix the alignment here as per checkpatch:
>> CHECK: Alignment should match open parenthesis
>> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>> +                       size_t count, loff_t *ppos)
>>
> 
> I'm not sure why I don't see that by checkpatch, but it looks that it
> is actually misalignment there, I would re-check all indents in
> source. Thanks.

You need to pass --strict to checkpatch to see it.

> 
>>>   {
>>>          unsigned int val;
>>> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
>>>          if (kstrtouint_from_user(data, count, 0, &val))
>>>                  return -EINVAL;
>>>          if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
>>> -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
>>> +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
>>>          else
>>>                  return -EINVAL;
>>>          return count;
>>>   }
>>>
Zong Li Sept. 6, 2022, 6:51 a.m. UTC | #6 
On Tue, Sep 6, 2022 at 2:23 PM <Conor.Dooley@microchip.com> wrote:
>
> On 06/09/2022 02:44, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > <Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道：
> >>
> >> Noticed a another thing, sorry..
> >>
> >> On 05/09/2022 09:31, Zong Li wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> From: Greentime Hu <greentime.hu@sifive.com>
> >>>
> >>> Since composable cache may be L3 cache if pL2 cache exists, we should use
> >>> its original name composable cache to prevent confusion.
> >>>
> >>> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> >>> table.
> >>>
> >>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> >>> Signed-off-by: Zong Li <zong.li@sifive.com>
> >>> ---
> >>>   drivers/soc/sifive/Kconfig                    |   6 +-
> >>>   drivers/soc/sifive/Makefile                   |   2 +-
> >>>   .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
> >>>   .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
> >>>   4 files changed, 94 insertions(+), 93 deletions(-)
> >>>   rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
> >>>   rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
> >>>
> >>
> >>> -static ssize_t l2_write(struct file *file, const char __user *data,
> >>> +static ssize_t ccache_write(struct file *file, const char __user *data,
> >>>                          size_t count, loff_t *ppos)
> >>
> >> You need to fix the alignment here as per checkpatch:
> >> CHECK: Alignment should match open parenthesis
> >> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
> >> +static ssize_t ccache_write(struct file *file, const char __user *data,
> >> +                       size_t count, loff_t *ppos)
> >>
> >
> > I'm not sure why I don't see that by checkpatch, but it looks that it
> > is actually misalignment there, I would re-check all indents in
> > source. Thanks.
>
> You need to pass --strict to checkpatch to see it.

Many thanks for the tip, I can see the message after applying the option.

>
> >
> >>>   {
> >>>          unsigned int val;
> >>> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
> >>>          if (kstrtouint_from_user(data, count, 0, &val))
> >>>                  return -EINVAL;
> >>>          if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> >>> -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> >>> +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
> >>>          else
> >>>                  return -EINVAL;
> >>>          return count;
> >>>   }
> >>>
>
diff mbox series

Patch

diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..ed4c571f8771 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -2,9 +2,9 @@ 
 
 if SOC_SIFIVE
 
-config SIFIVE_L2
-	bool "Sifive L2 Cache controller"
+config SIFIVE_CCACHE
+	bool "Sifive Composable Cache controller"
 	help
-	  Support for the L2 cache controller on SiFive platforms.
+	  Support for the composable cache controller on SiFive platforms.
 
 endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff77938f..1f5dc339bf82 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,3 @@ 
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_SIFIVE_L2)	+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c
similarity index 35%
rename from drivers/soc/sifive/sifive_l2_cache.c
rename to drivers/soc/sifive/sifive_ccache.c
index 59640a1d0b28..1b16a196547f 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -1,8 +1,8 @@ 
 // SPDX-License-Identifier: GPL-2.0
 /*
- * SiFive L2 cache controller Driver
+ * SiFive composable cache controller Driver
  *
- * Copyright (C) 2018-2019 SiFive, Inc.
+ * Copyright (C) 2018-2022 SiFive, Inc.
  *
  */
 #include <linux/debugfs.h>
@@ -11,33 +11,33 @@ 
 #include <linux/of_address.h>
 #include <linux/device.h>
 #include <asm/cacheinfo.h>
-#include <soc/sifive/sifive_l2_cache.h>
+#include <soc/sifive/sifive_ccache.h>
 
-#define SIFIVE_L2_DIRECCFIX_LOW 0x100
-#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
-#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
+#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
+#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
 
-#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
-#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
-#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120
+#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128
 
-#define SIFIVE_L2_DATECCFIX_LOW 0x140
-#define SIFIVE_L2_DATECCFIX_HIGH 0x144
-#define SIFIVE_L2_DATECCFIX_COUNT 0x148
+#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
+#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
+#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
 
-#define SIFIVE_L2_DATECCFAIL_LOW 0x160
-#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
-#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
+#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
+#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
+#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
 
-#define SIFIVE_L2_CONFIG 0x00
-#define SIFIVE_L2_WAYENABLE 0x08
-#define SIFIVE_L2_ECCINJECTERR 0x40
+#define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_WAYENABLE 0x08
+#define SIFIVE_CCACHE_ECCINJECTERR 0x40
 
-#define SIFIVE_L2_MAX_ECCINTR 4
+#define SIFIVE_CCACHE_MAX_ECCINTR 4
 
-static void __iomem *l2_base;
-static int g_irq[SIFIVE_L2_MAX_ECCINTR];
-static struct riscv_cacheinfo_ops l2_cache_ops;
+static void __iomem *ccache_base;
+static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
+static struct riscv_cacheinfo_ops ccache_cache_ops;
 
 enum {
 	DIR_CORR = 0,
@@ -49,7 +49,7 @@  enum {
 #ifdef CONFIG_DEBUG_FS
 static struct dentry *sifive_test;
 
-static ssize_t l2_write(struct file *file, const char __user *data,
+static ssize_t ccache_write(struct file *file, const char __user *data,
 			size_t count, loff_t *ppos)
 {
 	unsigned int val;
@@ -57,75 +57,76 @@  static ssize_t l2_write(struct file *file, const char __user *data,
 	if (kstrtouint_from_user(data, count, 0, &val))
 		return -EINVAL;
 	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
-		writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
+		writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
 	else
 		return -EINVAL;
 	return count;
 }
 
-static const struct file_operations l2_fops = {
+static const struct file_operations ccache_fops = {
 	.owner = THIS_MODULE,
 	.open = simple_open,
-	.write = l2_write
+	.write = ccache_write
 };
 
 static void setup_sifive_debug(void)
 {
-	sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
+	sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
 
 	debugfs_create_file("sifive_debug_inject_error", 0200,
-			    sifive_test, NULL, &l2_fops);
+			    sifive_test, NULL, &ccache_fops);
 }
 #endif
 
-static void l2_config_read(void)
+static void ccache_config_read(void)
 {
 	u32 regval, val;
 
-	regval = readl(l2_base + SIFIVE_L2_CONFIG);
+	regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
 	val = regval & 0xFF;
-	pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
+	pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
 	val = (regval & 0xFF00) >> 8;
-	pr_info("L2CACHE: No. of ways per bank: %d\n", val);
+	pr_info("CCACHE: No. of ways per bank: %d\n", val);
 	val = (regval & 0xFF0000) >> 16;
-	pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
+	pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
 	val = (regval & 0xFF000000) >> 24;
-	pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
+	pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
 
-	regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
-	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
+	regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+	pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
 }
 
-static const struct of_device_id sifive_l2_ids[] = {
+static const struct of_device_id sifive_ccache_ids[] = {
 	{ .compatible = "sifive,fu540-c000-ccache" },
 	{ .compatible = "sifive,fu740-c000-ccache" },
+	{ .compatible = "sifive,ccache0" },
 	{ /* end of table */ },
 };
 
-static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
+static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
 
-int register_sifive_l2_error_notifier(struct notifier_block *nb)
+int register_sifive_ccache_error_notifier(struct notifier_block *nb)
 {
-	return atomic_notifier_chain_register(&l2_err_chain, nb);
+	return atomic_notifier_chain_register(&ccache_err_chain, nb);
 }
-EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
+EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
 
-int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
+int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
 {
-	return atomic_notifier_chain_unregister(&l2_err_chain, nb);
+	return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
 }
-EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
+EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
 
-static int l2_largest_wayenabled(void)
+static int ccache_largest_wayenabled(void)
 {
-	return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
+	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
 }
 
 static ssize_t number_of_ways_enabled_show(struct device *dev,
 					   struct device_attribute *attr,
 					   char *buf)
 {
-	return sprintf(buf, "%u\n", l2_largest_wayenabled());
+	return sprintf(buf, "%u\n", ccache_largest_wayenabled());
 }
 
 static DEVICE_ATTR_RO(number_of_ways_enabled);
@@ -139,99 +140,99 @@  static const struct attribute_group priv_attr_group = {
 	.attrs = priv_attrs,
 };
 
-static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
+static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
 {
-	/* We want to use private group for L2 cache only */
+	/* We want to use private group for composable cache only */
 	if (this_leaf->level == 2)
 		return &priv_attr_group;
 	else
 		return NULL;
 }
 
-static irqreturn_t l2_int_handler(int irq, void *device)
+static irqreturn_t ccache_int_handler(int irq, void *device)
 {
 	unsigned int add_h, add_l;
 
 	if (irq == g_irq[DIR_CORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
-		pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
+		pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DirError interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
+		readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
 					   "DirECCFix");
 	}
 	if (irq == g_irq[DIR_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW);
 		/* Reading this register clears the DirFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+		readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
 					   "DirECCFail");
-		panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+		panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
 	}
 	if (irq == g_irq[DATA_CORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
-		pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
+		pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DataError interrupt sig */
-		readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
+		readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
 					   "DatECCFix");
 	}
 	if (irq == g_irq[DATA_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
-		pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
+		pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DataFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+		readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
 					   "DatECCFail");
 	}
 
 	return IRQ_HANDLED;
 }
 
-static int __init sifive_l2_init(void)
+static int __init sifive_ccache_init(void)
 {
 	struct device_node *np;
 	struct resource res;
 	int i, rc, intr_num;
 
-	np = of_find_matching_node(NULL, sifive_l2_ids);
+	np = of_find_matching_node(NULL, sifive_ccache_ids);
 	if (!np)
 		return -ENODEV;
 
 	if (of_address_to_resource(np, 0, &res))
 		return -ENODEV;
 
-	l2_base = ioremap(res.start, resource_size(&res));
-	if (!l2_base)
+	ccache_base = ioremap(res.start, resource_size(&res));
+	if (!ccache_base)
 		return -ENOMEM;
 
 	intr_num = of_property_count_u32_elems(np, "interrupts");
 	if (!intr_num) {
-		pr_err("L2CACHE: no interrupts property\n");
+		pr_err("CCACHE: no interrupts property\n");
 		return -ENODEV;
 	}
 
 	for (i = 0; i < intr_num; i++) {
 		g_irq[i] = irq_of_parse_and_map(np, i);
-		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
+		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
 		if (rc) {
-			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
+			pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
 			return rc;
 		}
 	}
 
-	l2_config_read();
+	ccache_config_read();
 
-	l2_cache_ops.get_priv_group = l2_get_priv_group;
-	riscv_set_cacheinfo_ops(&l2_cache_ops);
+	ccache_cache_ops.get_priv_group = ccache_get_priv_group;
+	riscv_set_cacheinfo_ops(&ccache_cache_ops);
 
 #ifdef CONFIG_DEBUG_FS
 	setup_sifive_debug();
 #endif
 	return 0;
 }
-device_initcall(sifive_l2_init);
+device_initcall(sifive_ccache_init);
diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_ccache.h
similarity index 12%
rename from include/soc/sifive/sifive_l2_cache.h
rename to include/soc/sifive/sifive_ccache.h
index 92ade10ed67e..4d4ed49388a0 100644
--- a/include/soc/sifive/sifive_l2_cache.h
+++ b/include/soc/sifive/sifive_ccache.h
@@ -1,16 +1,16 @@ 
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * SiFive L2 Cache Controller header file
+ * SiFive Composable Cache Controller header file
  *
  */
 
-#ifndef __SOC_SIFIVE_L2_CACHE_H
-#define __SOC_SIFIVE_L2_CACHE_H
+#ifndef __SOC_SIFIVE_CCACHE_H
+#define __SOC_SIFIVE_CCACHE_H
 
-extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
-extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
+extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
+extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
 
-#define SIFIVE_L2_ERR_TYPE_CE 0
-#define SIFIVE_L2_ERR_TYPE_UE 1
+#define SIFIVE_CCACHE_ERR_TYPE_CE 0
+#define SIFIVE_CCACHE_ERR_TYPE_UE 1
 
-#endif /* __SOC_SIFIVE_L2_CACHE_H */
+#endif /* __SOC_SIFIVE_CCACHE_H */