From patchwork Sat Sep 10 19:42:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 12972599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7F6FC6FA82 for ; Sat, 10 Sep 2022 19:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbiIJTnC (ORCPT ); Sat, 10 Sep 2022 15:43:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229593AbiIJTnA (ORCPT ); Sat, 10 Sep 2022 15:43:00 -0400 Received: from mail.baikalelectronics.com (mail.baikalelectronics.com [87.245.175.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CD1B542AE8; Sat, 10 Sep 2022 12:42:57 -0700 (PDT) Received: from mail (mail.baikal.int [192.168.51.25]) by mail.baikalelectronics.com (Postfix) with ESMTP id 3B6C5DA8; Sat, 10 Sep 2022 22:46:33 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 3B6C5DA8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baikalelectronics.ru; s=mail; t=1662839193; bh=7TgrrBgCuUaEkmFSDnpHiN+dhfwmj+gMu3USlRqeY7k=; h=From:To:CC:Subject:Date:In-Reply-To:References:From; b=Z//sd+4FxnyJYZdNI7i/VVDmeCSInOUAPEgHOpAmuMUxn+b1GfhsGu4aY4LSpLr+u Pz5mEH1JrWzBSE+Ofa0aOv3nYrTA3RbctJQGWAKeNKt2KGTm7exWwZI/qA69WCdpvG YMVL7box+ACf8vELnYyW5E+OerKFh4uZPFm5oNm4= Received: from localhost (192.168.168.10) by mail (192.168.51.25) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 10 Sep 2022 22:42:42 +0300 From: Serge Semin To: Rob Herring , Krzysztof Kozlowski , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter , Punnaiah Choudary Kalluri CC: Serge Semin , Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Manish Narani , Dinh Nguyen , Rob Herring , Krzysztof Kozlowski , , , , , Borislav Petkov Subject: [PATCH v2 03/19] EDAC/synopsys: Fix mci->scrub_cap field setting Date: Sat, 10 Sep 2022 22:42:21 +0300 Message-ID: <20220910194237.10142-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20220910194237.10142-1-Sergey.Semin@baikalelectronics.ru> References: <20220910194237.10142-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The mem_ctl_info.scrub_cap field is supposed to be set with the ECC scrub-related flags while the driver initializes it with the SCRUB_HW_SRC flag ID. It's definitely wrong, though hasn't caused any problem since the structure field isn't used by the EDAC core. Let's fix it anyway by using the SCRUB_FLAG_HW_SRC macro to initialize the field. Fixes: ae9b56e3996d ("EDAC, synps: Add EDAC support for zynq ddr ecc controller") Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 17960f7ca29b..c6f3b383e5ff 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -858,7 +858,7 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) /* Initialize controller capabilities and configuration */ mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; - mci->scrub_cap = SCRUB_HW_SRC; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; mci->scrub_mode = SCRUB_NONE; mci->edac_cap = EDAC_FLAG_SECDED;