| Message ID | 20221102084608.28894-2-shubhrajyoti.datta@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | edac: xilinx: Added EDAC support for Xilinx DDR controller | expand |
On 02/11/2022 04:46, Shubhrajyoti Datta wrote: > This patch adds device tree bindings for Xilinx Versal EDAC for DDR Do not use "This commit/patch". https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 > controller. > > Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- > > .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml > new file mode 100644 > index 000000000000..6717bc0f3be9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > + > +description: > + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ > + 4X memory interfaces. Versal DDR memory controller has an optional ECC support > + which correct single bit ECC errors and detect double bit ECC errors. > + > +properties: > + compatible: > + const: xlnx,versal-ddrmc-edac Drop "edac". That's a Linuxism. > + > + reg: > + items: > + - description: DDR Memory Controller registers > + - description: NOC registers corresponding to DDR Memory Controller > + > + reg-names: > + items: > + - const: ddrmc_base > + - const: ddrmc_noc_base Drop redundant parts from names, so these could be "base" and "noc" or "ddrmc" and "noc". Or anything a bit more reasonable... Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..6717bc0f3be9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc-edac + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: ddrmc_base + - const: ddrmc_noc_base + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc-edac"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "ddrmc_base", "ddrmc_noc_base"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + }; + };