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Mon, 16 Jan 2023 23:41:06 -0600 Received: from xhdshubhraj40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 16 Jan 2023 23:41:03 -0600 From: Shubhrajyoti Datta To: CC: , , , , , , , Subject: [PATCH v3 1/2] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC Date: Tue, 17 Jan 2023 11:10:59 +0530 Message-ID: <20230117054100.8377-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117054100.8377-1-shubhrajyoti.datta@amd.com> References: <20230117054100.8377-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT008:EE_|CY8PR12MB7124:EE_ X-MS-Office365-Filtering-Correlation-Id: 56028969-c83f-4f81-0905-08daf84d6fab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: j/8gqgMScShWpXKiE7FSXv++RC+zbYeYsBn+ipCCq/Yj1tVBxZk7tPoHXgrV49n/EVEHqAlO2WOEUd+fe746kAkpm6X+mo7hol0DKAvzCwHmKZs0kZe7gkag7PmrexpqEoJRdYcrHCCd+oxbhrpP601l0IEa1YcCdtut+zE5tv54DtPaJxWZakfSCrNQNO76bkuaPohg+LPrCiCy8bii9UbfTMdn4ClT2nI/8kS1W4gR5Uk58K/4L+2x8fRgT3dGaTfG+senXeTr+qHJmZjeYyo5VO9fNgV10duAkyTx9jkQuHS0yGNuPzW+jRz5pcE+AcpMrnsPQLF5lGa2+YQA4885vI0LWTkqSleVtNEbkfkSqvq0OZwxy6niHrG8VPp4xDaRSiBBZ9Q4GUhoWs6XEO9dQpk+/JM2jezJoDvZYhLrUWF2j01XFN7B++6iJT+Kche72NXNzR8s3cL6kSDt6HoR2YtSd0gl3ROxq8x9FnY9DiAl5/PvvqMkURGJ4XyDk/0uK2J7JoqS3iW5MJb36tjuoc1cwEu7yPIjj5yYLIyRvzQgVylEff8Y1wMIS//03LwtPpDtbhShGjG/eNhNPycCedBK3aCTL2dcSQkV6fjrCPUNYYbyoq681EsSEodVqVsMJ/nnpRjcFBpFzF1Yev7pf9Z//XoHx+kyHMCrirIv84A0TM5l6ZS0mWm7wFfuvBmazhO0mHT6XnTpVucuTwokF/5Xc2rInVBx7zxPt+WpquGfwV6rEwcZlTdxwOb+U4I8zhLXxtNXw4dPQWJOwcObct1W+7ri8YTrN4bneYU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(39860400002)(346002)(136003)(451199015)(46966006)(40470700004)(36840700001)(81166007)(356005)(40460700003)(36756003)(40480700001)(82310400005)(82740400003)(86362001)(966005)(70586007)(70206006)(6916009)(8676002)(26005)(336012)(4326008)(186003)(478600001)(1076003)(54906003)(2616005)(316002)(36860700001)(41300700001)(8936002)(47076005)(426003)(83380400001)(44832011)(2906002)(6666004)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 05:41:09.5527 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56028969-c83f-4f81-0905-08daf84d6fab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7124 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add device tree bindings for Xilinx Versal EDAC for DDR controller. Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta Reviewed-by: Krzysztof Kozlowski --- (no changes since v2) Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };