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Sun, 14 May 2023 12:24:36 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , , , Subject: [RESEND PATCH v6 1/2] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC Date: Sun, 14 May 2023 22:54:31 +0530 Message-ID: <20230514172432.12505-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230514172432.12505-1-shubhrajyoti.datta@amd.com> References: <20230514172432.12505-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000145BA:EE_|MW3PR12MB4569:EE_ X-MS-Office365-Filtering-Correlation-Id: a358d153-618e-474d-9da9-08db54a019ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: leGByuJL1aFVlQpPlZ6fgLMHlnNV0mQAFFIqq0YVBuC2C+vK3JwVCEORkFxw21aDEM9JtojdZr/aW48E2d0JiqJFwj/MNKLmj95trVnUMs4EgyFA11TUFewgE8R9Pp6dRPEHi8ZsP+2PnXREzQ4Ap7TEuBj9yEfPGQtXbGI+CkLR2G1hVEvy6ndwxfuB+UhXSuKT0ZzeEQEYHJkFSsV4t4pg6DCsTrtp7GBw+r1yIOZ8X6Ma2JrhvsD/GF6HGfG6oKw7gE69NnDVvsDcUOw2+kLuA8qoAS8wbxUFDpO4YYFH2AOakbygHlkCcmDMTor9Q/MIE1R/94my3/5m0n27vJTqr+wiL8j9CyXL9X0dozPY9EnI9dkD0gtaynW/w2QDkb2xQQWmuuKYwJBTbMICLzH3747IqTL5qtGy+ObEugYuQtoVSRjIpmGcOeHarBx5GRyJgnEA+40nxr/705DWvpGT0VyakyOM1v/Um3jwv/RmQCu7N1HvAlC0AhcsDOF5ZDzmMlD5jdRcK9+OzXhi7oShQHqeGFAg1/S6+mFPZekJPGtkzDU8mPcIIvcVENNTVM3xhe2tiq6ZtZ9W2gA1/htpLH3rW6O0aDKk30UCWhAK+L7JV9f77pcowtYIqzvmhsRpj0MlMJZ32u+LMgJviL2EpPXkLgORuxkFlVf8DwyAZAFB0MEz+gcLFfm60wWMFjxCuKTEGNiDa/5EK1xpxlMYdcWTwVnCVxl+7b3PUxul3t7Cr0WVqaVtId1AWI0nmgreT6+/yyemDyxKGmuwEIyhkvxfnafEmXlFyDoJsqU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199021)(46966006)(36840700001)(40470700004)(47076005)(41300700001)(336012)(426003)(966005)(82740400003)(2906002)(36756003)(40460700003)(2616005)(40480700001)(316002)(36860700001)(6666004)(4326008)(83380400001)(44832011)(26005)(70206006)(356005)(70586007)(82310400005)(81166007)(6916009)(86362001)(8936002)(7416002)(8676002)(5660300002)(54906003)(478600001)(186003)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2023 17:24:40.4897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a358d153-618e-474d-9da9-08db54a019ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000145BA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4569 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add device tree bindings for Xilinx Versal EDAC for DDR controller. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta --- (no changes since v2) Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };