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Tue, 13 Jun 2023 23:29:01 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , , , , Subject: [PATCH v7 1/2] dt-bindings: memory-controllers: Add support for Xilinx Versal EDAC for DDRMC Date: Wed, 14 Jun 2023 09:58:51 +0530 Message-ID: <20230614042852.5575-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230614042852.5575-1-shubhrajyoti.datta@amd.com> References: <20230614042852.5575-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|CY8PR12MB7289:EE_ X-MS-Office365-Filtering-Correlation-Id: ee91b95b-4ea2-41c7-74fd-08db6c8fe3ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FA0hBzKdozULM64l7hP5FhmL0jv7Gu9aLZ+mL8nuQLUjcOU9IN3mornP/fFr5sxa4lkoLuHR2GYWZt4nT3F/dMx0bBYuLIDy3vZFFQ40ranaJgxMHWq300CKDRVCba64sVezHAf049AWx0RP++aF0+iLrNnJAws85/friJ3ZC9ba3QOVWXMnSXwtFqrkwEKZKf6Br1WiW1Sq23FlxNf8g9gd6Ue8P5KkE4cMU2HJ6PUFFWxgQhr46VB4wkQlMwZYk9xPhTmM/VWF9NsaYqm5CfstkVtV70dGD62dAut4OfYxHamg4XqH85GP+fHgpeUS3CeUt7lvccF7FSmj01CfY7YKIfE9V1tUY94jSQ+9AKlhFeQ/67EkADBFsafI6M7dRpUqByuDo08kjunX/1CgYvPaS3Z8xr/O80WARgao1ovwECj13Mszn5sNzh1wMbQNKtve/zvwzbAxQMDH6lKsKECb/SogInuRT0vYt/9j+v6i85wuKnQ7XwvxBvOv9SqWnjfjn6kXiwZ++B886zLi7YIKnVJ51g7tESm2J5VPKB9+z45UPz26UCU9sf7HF8TdjJNeXsYw9JAiBf75IPiPLpXJzyfmAvkYbiVC0qrmT0KRM151SOfTW+zC6q6sB6Of/WKXnwjLxWlwWKtgZlxIFAh++D8nWTY2Cci6fqLAzR95dKRGjwTYQrIdsL4BE4COiaVA4QXzGbAmhMJJRaoN49akuHzPkgDIgYsXLh5Igx7SlzVvf1OlZ8VBS+LE+muvt4kJpWdDjDqGgC+GjJC28R5f8XnDhcwHxTv0CBFNqgQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(396003)(39860400002)(376002)(451199021)(36840700001)(40470700004)(46966006)(6916009)(7416002)(4326008)(44832011)(41300700001)(316002)(70206006)(70586007)(186003)(2906002)(54906003)(478600001)(8676002)(8936002)(5660300002)(6666004)(966005)(40460700003)(26005)(1076003)(81166007)(82740400003)(40480700001)(36860700001)(356005)(83380400001)(336012)(426003)(36756003)(47076005)(82310400005)(86362001)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jun 2023 04:29:05.8285 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee91b95b-4ea2-41c7-74fd-08db6c8fe3ac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7289 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add device tree bindings for Xilinx Versal EDAC for DDR controller. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta --- Changes in v7: Update the subject to add memory-controllers instead of edac Changes in v4: Update the reviewed by tag Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };