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Thu, 5 Oct 2023 05:12:51 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , , , , Subject: [PATCH v9 1/2] dt-bindings: memory-controllers: Add support for Xilinx Versal EDAC for DDRMC Date: Thu, 5 Oct 2023 15:42:41 +0530 Message-ID: <20231005101242.14621-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231005101242.14621-1-shubhrajyoti.datta@amd.com> References: <20231005101242.14621-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DF:EE_|CH2PR12MB4232:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d1baaac-eab7-431b-78d2-08dbc58ba4a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xylfc26VBkcv6adMwkydl3mbS1wX4Y488AekF/tnaA6bzmGJsckU7mdFQzKuA7XOtlV6EWW8IlBXabcWE50CxyMnoVuVK3OElVxteCYvFjGpiQUkZtVZlMwrG2K3PSXLIc4yBPL8RJlAu6WnIze3BmZ1iKgqVlfGn2nosgD8J2h4r4lutq9vQZkQ75ZFo246mcafpMJ4+31kNSF9/t3Zd+cC0CH+p57sDxGF/MI0xhaa49rB6GLjvlbfytQai7PsgOSfMOsOW8of0+olyWgTe2K6SrzvSAQ7PfYezxdaE8ZDhvy/jX/dnlqQN/SbLDbR23L26EItVtqDglSYudC3ysU3lMpgolmRmBCNAUJuWR9olPndYfyouRSNpDtDGlaaRAkzL0tpOIhU9kxYrlpzKrnR6Zop20mBRT1piYsCfVUfgYaNfnCh1FswOgiyVWcp81jVZMS4sFtcu0O2W4QpGzOlDR/jXqlsiQl192xmI3vwj6GzwHy545uvxqf0iyefuH2HtJ11mvEIXR9JYUdV+Z4YdLj5k6bIMYdeJqvMAOxQb6We3Yv8vCPG8CCsvb1KXZRgN+uCKgqevpQFWxYb3GehwZdmztcB2EMee4Axlsqjl7tQa4JX+AlHER+oxZTpgTU2XFTrRLX59xnngQ7ZuG92XfS0slFre92vCjpvrhwxVp3ppkAm0WTVBALRzzDVxM3+aCJ7QAHR7esopbAwzYIOO8jgDGurKHkoZvYM7265x6DQ/kG35ofj3Od9vQWgCNNdE/+hpA5xasLkHlQj4YAqwqoXrp3bu+U7lDbPwQE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(136003)(396003)(376002)(230922051799003)(64100799003)(451199024)(1800799009)(82310400011)(186009)(36840700001)(40470700004)(46966006)(2906002)(44832011)(7416002)(4326008)(5660300002)(8936002)(8676002)(41300700001)(70586007)(70206006)(2616005)(40460700003)(316002)(6916009)(54906003)(36860700001)(40480700001)(26005)(336012)(426003)(36756003)(6666004)(1076003)(356005)(81166007)(82740400003)(83380400001)(86362001)(47076005)(478600001)(966005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 10:12:55.6022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d1baaac-eab7-431b-78d2-08dbc58ba4a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4232 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add device tree bindings for Xilinx Versal EDAC for DDR controller. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta --- (no changes since v7) Changes in v7: Update the subject to add memory-controllers instead of edac Changes in v4: Update the reviewed by tag Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };