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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003F66.mail.protection.outlook.com (10.167.248.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 24 Jun 2024 21:20:21 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 24 Jun 2024 16:20:20 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v2 4/5] x86/mce: Define mce_prep_record() helpers for common and per-CPU fields Date: Mon, 24 Jun 2024 16:20:07 -0500 Message-ID: <20240624212008.663832-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240624212008.663832-1-yazen.ghannam@amd.com> References: <20240624212008.663832-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|SJ0PR12MB6808:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c9cbdab-3b48-498d-0df7-08dc949374a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|1800799021|82310400023|36860700010; X-Microsoft-Antispam-Message-Info: G111Tmizt6249eTFN8uG6/19FDDuWNrCQC1NAV+7d8Ab/Q+LRqXS+MmQTxa/BX13lqU4ID8+avJpeClp09negFgmNrn/ubsO7cYZlvG63hY4LE71/M5CD6dkyOFHNFKViDM1lKn2jcac4ujmlZGP0bS7eAc8iqFCwhOIOLf/CpccfuCwrx94SG6ecZg/KjcCD6/MaP1QztqOaL6nWrStXJcmoXtGbkBB/Jta7LgfRYvy0VtO/bV5CuZ4AvbG4bjWnVj9jPknsz4hmOfwZ4R8C+ebqEW0u6BdkaSpDzmYQW2eBCvRvZNjNOAxNuoaSdlE9LJUf6KC6lAMaicfkzyG8gjpR3NNn2f+gk2HX7LAS7pnKDSqGrJVfuFh8GhtCOojezn93s5/786t6smIuOuRT7zIc0CseJ4cjZB4n5vt0nT4Mp9Yo49kRhrPRsgxCe+fUVpbB9CYlzqAulp4pz0uerHwdBLrhnQ1W0I8yyPdp6y46o9oeEtl8GNqTVofvxPvMRk5xfSNqFwW+oIrNYcXtMT+f0/X1tVdMvA5lWYeW7cm4Xi5XtFqEkNMI8mqsQIAzDe0j/UlBAx4IS0sNo1n/0vxFmYzF2d2F7W2GzMtSXl8/hQcJOHoRBEwHM+WevybaXM5fDHLh7/gqv6oPNl3jkD4UZ3cMHzAnoIrV6QPvWuUvlcd+lNDjd+n8RSYonlGfFdDDNHHstKagOqoqwZ/x+EuYiB81+QEkOnnGIqCJfvaX8BLyx6zFh6m3DssynychbOfLataZFwOSxREwqTVLz0Wef1p1GQezAPkxFVUazWo579qwdotV1gIEH+yEWc9yAv4H1NJAfRufuU1MEHvU7jjGTy8qjjhFaD1+6M1+HzONfi1xyUS0nuodV/YdXuV93bLQhj12AdkXKMOnlgiNyEX8BnehqGCws+BIn8Fdj05PX9NVcP99G8/+xHdZseHpoQUoVdw0I+r+vsnpvjbq1L2VHEfsISSHaJKIqydbovISSrCBt4iOQ6wtlKiEqvZw/vgIkHxQkgVo8dyNGfRMXxqTxCE6pOtops4dUuR4Levy24bNZlyKEdo3hh/D0OJg1t1BMfrMYzSYo7RC5838xQokIV7NmlDM94rXUJ3rdkElwNF123f4wvxCbt6C+NbekrS8Mu+mZKzdjVeWcc5YTCZRvtrJEmjIEOKa9atoiOsHm44GjZZEmPFyvBUs7xUbd3M+wOKsAAi2kjazATueec7FhBfSPckEcn9f10Nimxo0A8psmbmOIv1f3f+mtpt49wFWXLSdHSa47q72gWBB4Vu25WBpWfEGDbph15Z2rt5dXk1CWju4zTYePJLat4FafUWqxGrBirg/ZpwAeRjgFM2p/JhEj00HA/uaMGf8do= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(1800799021)(82310400023)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 21:20:21.6580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c9cbdab-3b48-498d-0df7-08dc949374a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6808 Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_prep_record() for errors reported from ACPI. Split mce_prep_record() so that there is a helper function to gather common, i.e. not CPU-specific, information and another helper for CPU-specific information. Leave mce_prep_record() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240521125434.1555845-3-yazen.ghannam@amd.com v1->v2: * No change. arch/x86/kernel/cpu/mce/core.c | 34 ++++++++++++++++++++---------- arch/x86/kernel/cpu/mce/internal.h | 2 ++ 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index dd5192ef52e0..0133f88dfffb 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -117,20 +117,32 @@ static struct irq_work mce_irq_work; */ BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); -/* Do initial initialization of a struct mce */ -void mce_prep_record(struct mce *m) +void mce_prep_record_common(struct mce *m) { memset(m, 0, sizeof(struct mce)); - m->cpu = m->extcpu = smp_processor_id(); + + m->cpuid = cpuid_eax(1); + m->cpuvendor = boot_cpu_data.x86_vendor; + m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ - m->time = __ktime_get_real_seconds(); - m->cpuvendor = boot_cpu_data.x86_vendor; - m->cpuid = cpuid_eax(1); - m->socketid = cpu_data(m->extcpu).topo.pkg_id; - m->apicid = cpu_data(m->extcpu).topo.initial_apicid; - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); - m->ppin = cpu_data(m->extcpu).ppin; - m->microcode = boot_cpu_data.microcode; + m->time = __ktime_get_real_seconds(); +} + +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m) +{ + m->cpu = cpu; + m->extcpu = cpu; + m->apicid = cpu_data(m->extcpu).topo.initial_apicid; + m->microcode = cpu_data(m->extcpu).microcode; + m->ppin = cpu_data(m->extcpu).ppin; + m->socketid = cpu_data(m->extcpu).topo.pkg_id; +} + +/* Do initial initialization of a struct mce */ +void mce_prep_record(struct mce *m) +{ + mce_prep_record_common(m); + mce_prep_record_per_cpu(smp_processor_id(), m); } DEFINE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 01f8f03969e6..43c7f3b71df5 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -261,6 +261,8 @@ enum mca_msr { /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); +void mce_prep_record_common(struct mce *m); +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m);