diff mbox series

[v2,5/5] x86/mce: Use mce_prep_record() helpers for apei_smca_report_x86_error()

Message ID 20240624212008.663832-6-yazen.ghannam@amd.com (mailing list archive)
State New
Headers show
Series Rework mce_setup() | expand

Commit Message

Yazen Ghannam June 24, 2024, 9:20 p.m. UTC 
Current AMD systems can report MCA errors using the ACPI Boot Error
Record Table (BERT). The BERT entries for MCA errors will be an x86
Common Platform Error Record (CPER) with an MSR register context that
matches the MCAX/SMCA register space.

However, the BERT will not necessarily be processed on the CPU that
reported the MCA errors. Therefore, the correct CPU number needs to be
determined and the information saved in struct mce.

Use the newly defined mce_prep_record_*() helpers to get the correct
data.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20240521125434.1555845-4-yazen.ghannam@amd.com

v1->v2:
* Rebased on new changes from patches 1 and 2.

 arch/x86/kernel/cpu/mce/apei.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c
index 8e8ad63da5b6..7e60db2addec 100644
--- a/arch/x86/kernel/cpu/mce/apei.c
+++ b/arch/x86/kernel/cpu/mce/apei.c
@@ -101,12 +101,9 @@  int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
 	if (ctx_info->reg_arr_size < 48)
 		return -EINVAL;
 
-	mce_prep_record(&m);
-
-	m.extcpu   = cpu;
-	m.socketid = cpu_data(cpu).topo.pkg_id;
+	mce_prep_record_common(&m);
+	mce_prep_record_per_cpu(cpu, &m);
 
-	m.apicid = lapic_id;
 	m.bank = (ctx_info->msr_addr >> 4) & 0xFF;
 	m.status = *i_mce;
 	m.addr = *(i_mce + 1);