@@ -88,7 +88,7 @@
/* DDR ECC Quirks */
#define DDR_ECC_INTR_SUPPORT BIT(0)
#define DDR_ECC_DATA_POISON_SUPPORT BIT(1)
-#define DDR_ECC_INTR_SELF_CLEAR BIT(2)
+#define SYNPS_ZYNQMP_IRQ_REGS BIT(2)
/* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
/* ECC Configuration Registers */
@@ -526,7 +526,7 @@ static void enable_intr(struct synps_edac_priv *priv)
unsigned long flags;
/* Enable UE/CE Interrupts */
- if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
+ if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) {
writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
@@ -535,6 +535,10 @@ static void enable_intr(struct synps_edac_priv *priv)
spin_lock_irqsave(&priv->reglock, flags);
+ /*
+ * IRQs Enable/Disable flags have been available since v3.10a.
+ * This is noop for the older controllers.
+ */
writel(DDR_UE_MASK | DDR_CE_MASK,
priv->baseaddr + ECC_CLR_OFST);
@@ -546,7 +550,7 @@ static void disable_intr(struct synps_edac_priv *priv)
unsigned long flags;
/* Disable UE/CE Interrupts */
- if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
+ if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) {
writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
@@ -577,11 +581,7 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
priv = mci->pvt_info;
p_data = priv->p_data;
- /*
- * v3.0 of the controller has the ce/ue bits cleared automatically,
- * so this condition does not apply.
- */
- if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) {
+ if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) {
regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
if (!(regval & ECC_CE_UE_INTR_MASK))
@@ -598,8 +598,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
edac_dbg(3, "Total error count CE %d UE %d\n",
priv->ce_cnt, priv->ue_cnt);
- /* v3.0 of the controller does not have this register */
- if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
+
+ if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS)
writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
return IRQ_HANDLED;
@@ -913,7 +913,7 @@ static const struct synps_platform_data zynqmp_edac_def = {
.get_mtype = zynqmp_get_mtype,
.get_dtype = zynqmp_get_dtype,
.get_ecc_state = zynqmp_get_ecc_state,
- .quirks = (DDR_ECC_INTR_SUPPORT
+ .quirks = (DDR_ECC_INTR_SUPPORT | SYNPS_ZYNQMP_IRQ_REGS
#ifdef CONFIG_EDAC_DEBUG
| DDR_ECC_DATA_POISON_SUPPORT
#endif
@@ -925,7 +925,7 @@ static const struct synps_platform_data synopsys_edac_def = {
.get_mtype = zynqmp_get_mtype,
.get_dtype = zynqmp_get_dtype,
.get_ecc_state = zynqmp_get_ecc_state,
- .quirks = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR
+ .quirks = (DDR_ECC_INTR_SUPPORT
#ifdef CONFIG_EDAC_DEBUG
| DDR_ECC_DATA_POISON_SUPPORT
#endif
The DDR_ECC_INTR_SELF_CLEAR quirk flag was initially added in the commit f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR") in order to distinguish the ZynqMP DDRC (based on DW uMCTL2 DDRC v2.40a) and the announced in that commit Synopsys DDR controller v3.80a. The selected name is misleading for the next reasons: 1. None of the Synopsys DW uMCTL2 DDR IP-core has the UE/CE IRQs auto or self cleared. The IRQ signals (ecc_corrected_err_intr and ecc_uncorrected_err_intr) are cleared together with the rest of the ECC error data by means of writing 1's to the respective ECCCLR bits. It worked like that in DW uMCTL2 DDRC v2.x IP-core and it's still true for the modern DW uMCTL2 DDRC v3.x. 2. The IRQ-related registers accessed unless the denoted quirk is specified are actually Xilinx Zynq-specific. None of the Synopsys DW uMCTL DDRC IP-core have any registers at the offsets 0x20200/0x20208/0x2020C. The most modern DW uMCTL2 DDRC v3.91a IP-core available has CSRs space end at the 0x43dc offset. The older IP-cores have even smaller registers space. 3. What was actually introduced in the DW uMCTL2 DDRC v3.10 by Synopsys is the IRQ enable flags which older DW uMCTL2 DDRC IP-core didn't have. They were added to the ECCCLR register (the CSR was also renamed to ECCCTL in the v3.10 IP-core HW databook). So since then there have been no point in having a vendor-specific IRQs masking solution like described in 2. and the IRQ signal can be now shared even for the native DW uMCTL2 DDR controllers. So let's harmonize the quirked IRQs code based on the statements above: rename the DDR_ECC_INTR_SELF_CLEAR quirk flag to SYNPS_ZYNQMP_IRQ_REGS thus indicating the ZynqMP-specific IRQ CSRs; add the new quirk flag to the ZynqMP platform data; drop the misleading comments about the auto-cleared ue/ce flags; add a comment about the new IRQ enable flags added in v3.10 IP-core. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> --- Changelog v4: - This is a new patch detached from [PATCH v3 01/17] EDAC/synopsys: Fix native uMCTL2 IRQs handling procedure --- drivers/edac/synopsys_edac.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-)