| Message ID | 20240709-imx95_edac-v1-6-3e9c146c1b01@nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | EDAC: fsl-ddr, add imx9 support | expand |
> Subject: [PATCH 6/6] arm64: dts: imx93: add ddr edac support > > Add ddr edac support for imx93. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx93.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi > b/arch/arm64/boot/dts/freescale/imx93.dtsi > index 4a3f42355cb8f..6faba848fe286 100644 > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > @@ -1279,6 +1279,14 @@ usbmisc2: usbmisc@4c200200 { > #index-cells = <1>; > }; > > + memory-controller@4e300000 { > + compatible = "nxp,imx9-memory-controller"; > + reg = <0x4e300000 0x800>, <0x4e301000 > 0x1000>; > + reg-names = "ctrl", "inject"; > + interrupts = <GIC_SPI 91 > IRQ_TYPE_LEVEL_HIGH>; > + little-endian; > + }; > + > ddr-pmu@4e300dc0 { Should the ddr-pmu be part of memory controller? Regards, Peng. > compatible = "fsl,imx93-ddr-pmu"; > reg = <0x4e300dc0 0x200>; > > -- > 2.34.1 >
On Wed, Jul 10, 2024 at 02:25:02AM +0000, Peng Fan wrote: > > Subject: [PATCH 6/6] arm64: dts: imx93: add ddr edac support > > > > Add ddr edac support for imx93. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx93.dtsi | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi > > b/arch/arm64/boot/dts/freescale/imx93.dtsi > > index 4a3f42355cb8f..6faba848fe286 100644 > > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > > @@ -1279,6 +1279,14 @@ usbmisc2: usbmisc@4c200200 { > > #index-cells = <1>; > > }; > > > > + memory-controller@4e300000 { > > + compatible = "nxp,imx9-memory-controller"; > > + reg = <0x4e300000 0x800>, <0x4e301000 > > 0x1000>; > > + reg-names = "ctrl", "inject"; > > + interrupts = <GIC_SPI 91 > > IRQ_TYPE_LEVEL_HIGH>; > > + little-endian; > > + }; > > + > > ddr-pmu@4e300dc0 { > > Should the ddr-pmu be part of memory controller? imx9-memory-controller is actually EDAC, which independent with ddr pmu. I think ddr-pmu should be seperate node. Frank > > Regards, > Peng. > > > compatible = "fsl,imx93-ddr-pmu"; > > reg = <0x4e300dc0 0x200>; > > > > -- > > 2.34.1 > > >
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 4a3f42355cb8f..6faba848fe286 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1279,6 +1279,14 @@ usbmisc2: usbmisc@4c200200 { #index-cells = <1>; }; + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>;
Add ddr edac support for imx93. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- arch/arm64/boot/dts/freescale/imx93.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)