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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00001507.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Tue, 30 Jul 2024 18:30:13 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 30 Jul 2024 13:30:10 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH v3 2/3] x86/mce: Define mce_prep_record() helpers for common and per-CPU fields Date: Tue, 30 Jul 2024 13:29:57 -0500 Message-ID: <20240730182958.4117158-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240730182958.4117158-1-yazen.ghannam@amd.com> References: <20240730182958.4117158-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|PH7PR12MB6859:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b74e8b0-dc71-46e2-ef64-08dcb0c5a6f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: su5vDcc0274DRDRHGw+clI6B3DAioQDsiGR5+YScuaHxma9R/d9pBKTYAZiWL18ciJos0r04ZGS4gj8FFfu7hpKps/mKDLtuEHXOUIb295D0ShTgJjJZdbVB5osgluFVHE3DSTcrbyZcHTbrrYESDsjYRh+3SUFOnGujwdMYIvMIBeCLn9IjQxa7vujrMvPEHZx+sugDdaL7vRpdz2drc6Xo7N1fTFgRNEdMNjqcH/SVU5zgam/YAv2FHAW7jmi3pIxDtYTE5MYKULypCyFJxPT8/m+kkVt89UpN3FprecSQY4BREq2pI5GJxYajglIvUxfIHrYnvi2FJ7ZS3Nu9r+2iQAGr9kWXoG9/q1cQ/QWYxb+P/MakR/YvHneLSj9L9/uY5LVJdyEXY93y+itJwD6XJn/zkWbj2igxXxXE3fGH1j9HXxVXFbE9c3wXacY38qCyXVOr+wnJEZNaNvjD46G1lC70FuY9Na6bX2vA/ZzrWLOzEjlMv6eYDhabfZYttuGdpcqoTha63w9zTQNXMWaGpwlsbLwasm23Dw1mq0Nn6pNpH1HKsFnroiH+JPDEBLTlWP2/4QQ58VoAHbe/wTxpKs5Uh9f0XJ9ZrBhVQDz/cJW/uzMFU8GWpH3jD9xWXSPWlLxKaAtwbUNjvTyDdQSWUjDm6Je8j9V0xI1nhNgh0nu4tEn0PS1cOzgE5MSB+O+LrwmphVErB5REcFJnblmDhjQ/LqXrNWvF1lMkmQHv805OdfqIs8ID/UbN5N/5x5K+isDsNTAI2+3GyGy6NrjBN/kVGoeSZOKMbe3Fb0b8mQe1uYl97uPVf/EnNUONU8AQA/GYhQvhstXmNFHaE8+yhKd5uDleOp/Xthq+MhSay6n6RwaArfNLRlI6twXDZgaznmOrioQ1jj20hZL+gJ4QS0YyX9TZPAR8D89aEeKzPFr55AH0EqQbHQgY3CJu1B5uwVIMLzsIrFZyfH7346I6tw3VRdulMRCeStuYdEeGmoIkyW4YkZ5IRYc8Lt0aDDBVEvZQHj4lDT1BRDoGBSFUT/+li8VZG68Iwdpe1dYXc3wp4bBnARM6oTRU1qENZLzKi2+Ur4STl1a+IcwdnQVT0aKqU9vlDk/VTAqsY0tORC+2mVEw//ykxTAJHFCaFNC2nZaROHYMeYJr/OAy+/vi+XTC5MmAv+ocGC+CeFhrkyai0ua9p3IBDbBH0qYQJnxvHDqZf68o2V9ycD3OhNGMPcPWguC8bWCn3U/4FhGt3X1Tpxe1OX19hSl96rhV41ilSXy49+We/gjD7HR5PLDL0a625LdgdXzhi6Eogt2GkDHLrnbLOAFK9+m9LUfr+9EIEv5kCsANHjJrzgGcTDPy9GGg9rPNt6cji9H3OgT/vTI7GSCxDr5YplIRG/yENEx/mAzNQu7x85pj/smqEw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 18:30:13.5102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b74e8b0-dc71-46e2-ef64-08dcb0c5a6f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6859 Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_prep_record() for errors reported from ACPI. Split mce_prep_record() so that there is a helper function to gather common, i.e. not CPU-specific, information and another helper for CPU-specific information. Leave mce_prep_record() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20240624212008.663832-5-yazen.ghannam@amd.com v2->v3: * Use topology_*() helpers (Nikolay). v1->v2: * No change. arch/x86/kernel/cpu/mce/core.c | 34 ++++++++++++++++++++---------- arch/x86/kernel/cpu/mce/internal.h | 2 ++ 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index dd5192ef52e0..2a938f429c4d 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -117,20 +117,32 @@ static struct irq_work mce_irq_work; */ BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); -/* Do initial initialization of a struct mce */ -void mce_prep_record(struct mce *m) +void mce_prep_record_common(struct mce *m) { memset(m, 0, sizeof(struct mce)); - m->cpu = m->extcpu = smp_processor_id(); + + m->cpuid = cpuid_eax(1); + m->cpuvendor = boot_cpu_data.x86_vendor; + m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ - m->time = __ktime_get_real_seconds(); - m->cpuvendor = boot_cpu_data.x86_vendor; - m->cpuid = cpuid_eax(1); - m->socketid = cpu_data(m->extcpu).topo.pkg_id; - m->apicid = cpu_data(m->extcpu).topo.initial_apicid; - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); - m->ppin = cpu_data(m->extcpu).ppin; - m->microcode = boot_cpu_data.microcode; + m->time = __ktime_get_real_seconds(); +} + +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m) +{ + m->cpu = cpu; + m->extcpu = cpu; + m->apicid = cpu_data(cpu).topo.initial_apicid; + m->microcode = cpu_data(cpu).microcode; + m->ppin = topology_ppin(cpu); + m->socketid = topology_physical_package_id(cpu); +} + +/* Do initial initialization of a struct mce */ +void mce_prep_record(struct mce *m) +{ + mce_prep_record_common(m); + mce_prep_record_per_cpu(smp_processor_id(), m); } DEFINE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 01f8f03969e6..43c7f3b71df5 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -261,6 +261,8 @@ enum mca_msr { /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); +void mce_prep_record_common(struct mce *m); +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m);