From patchwork Mon Oct 14 07:53:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony W Wang-oc X-Patchwork-Id: 13834296 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 617AB14A4F7 for ; Mon, 14 Oct 2024 08:09:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.0.225.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728893393; cv=none; b=jotGyfadpAA+RriDpwc0exlpDTASn9Ux/953xLgFa4zLJARyjKbwICgFWX4WuRLasgFndv+dnsQz9Ezj7386GVNksCTDCj8ewAJ05V8RauiEM3V3LFf+V8SjYdmDviLE72fpmAbu6+i1Fs8xNY8pHBphOyay/y9AecvnSFYZUaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728893393; c=relaxed/simple; bh=yfftzBKL6yLzE3TQ1mgzMxva4dfjb8xcfY8+jcaTBjc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AxyQalJ4cq01IyjwMF5un6NEcrZ0dcwccas7fBw1iiRMn6U60yoOGm//Q0DSNKQuBaEtCxjlwN5GRsMXFdQEHHYPjouSfnmnAr7b1hXjMoD4CaMlIJDKR2mQj1+JjOpxOHW/8q+L58+999jdDhLSTcw7ChmSHeoxxSXvBHmLMi4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=210.0.225.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1728893375-086e23455901f30001-QCVQLf Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx1.zhaoxin.com with ESMTP id jsZS3Z3bnanlKkzW (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Mon, 14 Oct 2024 16:09:35 +0800 (CST) X-Barracuda-Envelope-From: TonyWWang-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXSHMBX1.zhaoxin.com (10.28.252.163) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Oct 2024 16:09:34 +0800 Received: from ZXSHMBX1.zhaoxin.com ([fe80::3066:e339:e3d6:5264]) by ZXSHMBX1.zhaoxin.com ([fe80::3066:e339:e3d6:5264%7]) with mapi id 15.01.2507.039; Mon, 14 Oct 2024 16:09:34 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from localhost.localdomain (10.32.65.165) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 14 Oct 2024 15:53:08 +0800 From: Tony W Wang-oc To: , , , , , , , , , CC: , , , Lyle Li Subject: [PATCH v5 1/4] x86/mce: Add Centaur vendor to support Zhaoxin MCA Date: Mon, 14 Oct 2024 15:53:15 +0800 X-ASG-Orig-Subj: [PATCH v5 1/4] x86/mce: Add Centaur vendor to support Zhaoxin MCA Message-ID: <20241014075318.1936-2-TonyWWang-oc@zhaoxin.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241014075318.1936-1-TonyWWang-oc@zhaoxin.com> References: <20240923073311.4290-1-TonyWWang-oc@zhaoxin.com> <20241014075318.1936-1-TonyWWang-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 10/14/2024 4:09:33 PM X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1728893375 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 2629 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.131784 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: Lyle Li Zhaoxin consists of two vendors, X86_VENDOR_ZHAOXIN and X86_VENDOR_CENTAUR. Add the missing Centaur vendor to support Zhaoxin MCA. Signed-off-by: Lyle Li Signed-off-by: Tony W Wang-oc Reviewed-by: Qiuxu Zhuo --- arch/x86/kernel/cpu/mce/core.c | 9 +++++++-- arch/x86/kernel/cpu/mce/intel.c | 3 ++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2a938f429c4d..1b647869c320 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -508,6 +508,7 @@ bool mce_usable_address(struct mce *m) case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: return intel_mce_usable_address(m); default: @@ -525,6 +526,7 @@ bool mce_is_memory_error(struct mce *m) case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: /* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes * @@ -1254,7 +1256,8 @@ static noinstr bool mce_check_crashing_cpu(void) mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) { if (mcgstatus & MCG_STATUS_LMCES) return false; } @@ -1528,7 +1531,8 @@ noinstr void do_machine_check(struct pt_regs *regs) * on Intel, Zhaoxin only. */ if (m.cpuvendor == X86_VENDOR_INTEL || - m.cpuvendor == X86_VENDOR_ZHAOXIN) + m.cpuvendor == X86_VENDOR_ZHAOXIN || + m.cpuvendor == X86_VENDOR_CENTAUR) lmce = m.mcgstatus & MCG_STATUS_LMCES; /* @@ -2099,6 +2103,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) break; case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: mce_zhaoxin_feature_clear(c); break; diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6bf69a..b7e67f4f7edd 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -88,7 +88,8 @@ static int cmci_supported(int *banks) * makes sure none of the backdoors are entered otherwise. */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN && + boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) return 0; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)