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[114.74.229.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211056edb4csm25014455ad.58.2024.11.01.13.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Nov 2024 13:43:11 -0700 (PDT) From: Orange Kao To: tony.luck@intel.com, qiuxu.zhuo@intel.com Cc: bp@alien8.de, james.morse@arm.com, orange@kaosy.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, mchehab@kernel.org, rric@kernel.org, Orange Kao Subject: [PATCH 2/2] EDAC/igen6: Add polling support Date: Fri, 1 Nov 2024 20:41:14 +0000 Message-ID: <20241101204211.414664-3-orange@aiven.io> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241101204211.414664-1-orange@aiven.io> References: <20241101204211.414664-1-orange@aiven.io> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 I have a PC with Intel N100 (with PCI device 8086:461c, DID_ADL_N_SKU4) but interrupt does not seems to work, even with the following configuration in BIOS. I am not sure if this is caused by a BIOS bug or not. In-Band ECC Support: Enabled In-Band ECC Operation Mode: 2 (make all requests protected and ignore range checks) IBECC Error Injection Control: Inject Correctable Error on insertion counter Error Injaction Insertion Count: 251658240 (0xf000000) This commit tried to add polling support. Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 07dacf8c10be..5027070410a5 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -1170,6 +1170,19 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64 *mchbar) return -ENODEV; } +static void igen6_check(struct mem_ctl_info *mci) +{ + struct igen6_imc *imc = mci->pvt_info; + + /* errsts_clear() isn't NMI-safe. Delay it in the IRQ context */ + u64 ecclog = ecclog_read_and_clear(imc); + if (!ecclog) + return; + if (!ecclog_gen_pool_add(imc->mc, ecclog)) + irq_work_queue(&ecclog_irq_work); + +} + static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev) { struct edac_mc_layer layers[2]; @@ -1211,6 +1224,9 @@ static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev) mci->edac_cap = EDAC_FLAG_SECDED; mci->mod_name = EDAC_MOD_STR; mci->dev_name = pci_name(pdev); + if (edac_op_state == EDAC_OPSTATE_POLL) { + mci->edac_check = igen6_check; + } mci->pvt_info = &igen6_pvt->imc[mc]; imc = mci->pvt_info; @@ -1450,7 +1466,9 @@ static int __init igen6_init(void) if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) return -EBUSY; - edac_op_state = EDAC_OPSTATE_NMI; + if (edac_op_state == EDAC_OPSTATE_INVAL) { + edac_op_state = EDAC_OPSTATE_NMI; + } rc = pci_register_driver(&igen6_driver); if (rc) @@ -1474,3 +1492,6 @@ module_exit(igen6_exit); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Qiuxu Zhuo"); MODULE_DESCRIPTION("MC Driver for Intel client SoC using In-Band ECC"); + +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI. Default=1");