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Fri, 22 Nov 2024 04:06:38 -0600 From: Shubhrajyoti Datta To: , , CC: , , , , , , , , Subject: [PATCH 2/3] cdx: add DDRMC commands Date: Fri, 22 Nov 2024 15:36:24 +0530 Message-ID: <20241122100625.24571-3-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241122100625.24571-1-shubhrajyoti.datta@amd.com> References: <20241122100625.24571-1-shubhrajyoti.datta@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: shubhrajyoti.datta@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|MN2PR12MB4239:EE_ X-MS-Office365-Filtering-Correlation-Id: 74a1195d-f9e4-4538-c8aa-08dd0add5e3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: X5DYAN8zR9F868CrVTYtZTDb4wBQ3xZ8XhwDP7qL/i4CZE0ZJkTSzPgWGcxm38khhuKiNYb//f1HM96y9vCp+9hxXWD5ePZyE8p90yWINkW3gXgn42wRk9OsUtQwOADmwaGdcurOAeL4hlN+YpeHGrS+YbhTFVPTbGfVs5KirN6HwuKxTzdyjeu4bKgm+6E8upmf8YWdWxddN9lMMw1MmSs+gekhArXVCeJcFx92xFxEk26OuMaN9bkngctfiAMzhQcPxa25mqCUOYB4fGLMeVabIuENeuzhB5Vmu4JnFQa78Lof015xSuTdtTNN7p2pXsqI9oylDcjmTLP+rLEoSnHRk/We2INedwnvFuN39AiF1z6uZf9vBUnruxU+LHCQZ7IWt6CY1dzAdR6vC5LOvX+tOpXHPEqBVSnR39yj6H0VQo6FVKx0k/0gfKOjiKJWnN8jgtO8CeyZXuFHcoHfGhowxwIH40jvBcTqwmG8NWlICuc67NFJoH4aVrE7x1m1QM6xKM5Y1MQrc4GutO26+/1kUHZ0BRAj3sfFItB59cZjOahoxb4MF4KyLBcE8niBBFlaXfxbQ5zW+LnKD4WNdtfStV8GlQxnBHh73ZkKpqy0HjkcsZx7TTSIjbSk0t4TaSnPAGc95Y5lx7H9dk14TnqgjJk8o1wIgSZyLoV3TYbLNCVfa1GrjPP8+J1wW5BCiisVfqGv6yzksB83WQB/o5v/w5hrdvEegoaI185YaY7gjXpw2njGeiaJiUQvINW/c9nH8nGzS7cyU8pdWB1Jn2TSExfdu/YnzORdd11VQ96ltwcTU9HEXLBmliJGaQGLpoLzxZyelALHAnqcs/GUctFnrKQWCQ6YU3aH0TkiaD6an3RLbyfMv9ojiHxAoetOKvt6aDsU6x7D1/atWQoxUcW6B1D45bFsXlvQQJ7ztmgBVKq2Txv8ZGn+Pgr2ugPZ4do0G3cXfDecvhAAi5FbMtnynsn85la+7rzcg1nF7DQflrl2uXls6clwrWsnyWJ3+pfNW9Hn0p6A5dgBN1xPt5vcZMXSwYikhwL5zMV0bwRh9Islb+ImF6E6JHLldaUCb3Nbq4fWfDMUBAhZHfoiPI/P4kDbESMb+ySvF3l1sDiXgqNNKU6rfv6OFmFhT2lL87zDppLLgGvhmErql6gqRGgJawab0lN2uA9NXqxXHbrhYJ6oWN3ZLDaqu/pmaq6d91975QF7VzHFFp9VWtgTzZaFEgD/oJqXNP7JtEljkNwBt7NWhF70cciKY6hA5fYXP/usuLLzVNwZIjbTfMO4+4xAb5vUV5HaLorb7J3qGlb4T7XFJ19jQsdtoc1ROBqMgS1wP19Fj0f0HnW0KH1KwvHOXqfLD32cdd+4yH7kaxCWQ76u7jcjFgjd+qtD4dFuZvIYwaEjLHsufByJoB5K4A== X-Forefront-Antispam-Report: CIP:165.204.84.12;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:atlvpn-bp.amd.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2024 10:06:44.0567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74a1195d-f9e4-4538-c8aa-08dd0add5e3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4239 Add the commands for getting the DDRMC properties. Signed-off-by: Shubhrajyoti Datta --- drivers/cdx/controller/mc_cdx_pcol.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/cdx/controller/mc_cdx_pcol.h b/drivers/cdx/controller/mc_cdx_pcol.h index 832a44af963e..174270e148f3 100644 --- a/drivers/cdx/controller/mc_cdx_pcol.h +++ b/drivers/cdx/controller/mc_cdx_pcol.h @@ -302,6 +302,12 @@ #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_OFST 0 #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_LEN 4 +/* Number of registers */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_OFST 0 +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_LEN 4 +/* Number of registers for the DDR controller */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_REGISTER_VALUES_OFST 4 +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_REGISTER_VALUES_LEN 4 /***********************************/ /* * MC_CMD_CDX_BUS_GET_DEVICE_CONFIG @@ -587,6 +593,16 @@ /* MC_CMD_CDX_DEVICE_CONTROL_SET_OUT msgresponse */ #define MC_CMD_CDX_DEVICE_CONTROL_SET_OUT_LEN 0 +/***********************************/ +/* MC_CMD_EDAC_GET_DDR_CONFIG + * Provides detailed configuration for the DDR controller of the given index. + */ +#define MC_CMD_EDAC_GET_DDR_CONFIG 0x3 + +/* MC_CMD_EDAC_GET_DDR_CONFIG_IN msgrequest */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_OFST 0 +#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_LEN 4 + /***********************************/ /* * MC_CMD_CDX_DEVICE_CONTROL_GET