| Message ID | 20250102174434.17677-5-shubhrajyoti.datta@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | EDAC: Versal NET: Add support for error notification | expand |
On 02/01/2025 18:44, Shubhrajyoti Datta wrote: > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > + > +description: > + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 > + compact and extended memory interfaces. Versal NET DDR memory controller has an optional ECC support Please wrap code according to coding style (checkpatch is not a coding style description, but only a tool). > + which correct single bit ECC errors and detect double bit ECC errors. > + It also has support for reporting other errors like MMCM (Mixed-Mode Clock > + Manager) errors and General software errors. > + > +properties: > + compatible: > + const: amd,versal-net-ddrmc5-1.0 1.0 looks redundant. Usually SoC does not change... Anyway, commit msg should explain why 1.0 is needed (IOW, why exception is justified). > + > + amd,rproc: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle to the remoteproc_r5 rproc node using which APU interacts > + with remote processor. APU primarily communicates with the RPU for > + accessing the DDRMC address space and getting error notification. > + > +required: > + - compatible > + - amd,rproc > + > +additionalProperties: false > + > +examples: > + - | > + memory-controller { > + compatible = "amd,versalnet-ddrmc"; And this one? Best regards, Krzysztof
On Thu, 02 Jan 2025 23:14:33 +0530, Shubhrajyoti Datta wrote: > Add device tree bindings for AMD Versal NET EDAC for DDR controller. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- > > Changes in v4: > Update the compatible > align the example > Enhance the description for rproc > > Changes in v2: > - rename EDAC to memory controller > - update the compatible name > - Add remote proc handle > - Read the data width from the registers > - Remove the dwidth, rank and channel number the same is read from the RpMsg. > > .../amd,versal-net-ddrmc5-1.0.yaml | 41 +++++++++++++++++++ > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5-1.0.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5-1.0.example.dtb: /example-0/memory-controller: failed to match any schema with compatible: ['amd,versalnet-ddrmc'] doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250102174434.17677-5-shubhrajyoti.datta@amd.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On Thu, Jan 2, 2025 at 11:31 PM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On 02/01/2025 18:44, Shubhrajyoti Datta wrote: > > + > > +maintainers: > > + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > > + > > +description: > > + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 > > + compact and extended memory interfaces. Versal NET DDR memory controller has an optional ECC support > > Please wrap code according to coding style (checkpatch is not a coding > style description, but only a tool). Will fix . > > > > + which correct single bit ECC errors and detect double bit ECC errors. > > + It also has support for reporting other errors like MMCM (Mixed-Mode Clock > > + Manager) errors and General software errors. > > + > > +properties: > > + compatible: > > + const: amd,versal-net-ddrmc5-1.0 > > 1.0 looks redundant. Usually SoC does not change... Anyway, commit msg > should explain why 1.0 is needed (IOW, why exception is justified). > > > + I will change it to const: amd,versal-net-ddrmc5 instead.
diff --git a/Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5-1.0.yaml b/Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5-1.0.yaml new file mode 100644 index 000000000000..4c81e30f4818 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5-1.0.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/amd,versal-net-ddrmc5-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET Memory Controller + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 + compact and extended memory interfaces. Versal NET DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + It also has support for reporting other errors like MMCM (Mixed-Mode Clock + Manager) errors and General software errors. + +properties: + compatible: + const: amd,versal-net-ddrmc5-1.0 + + amd,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. APU primarily communicates with the RPU for + accessing the DDRMC address space and getting error notification. + +required: + - compatible + - amd,rproc + +additionalProperties: false + +examples: + - | + memory-controller { + compatible = "amd,versalnet-ddrmc"; + amd,rproc = <&remoteproc_r5>; + };
Add device tree bindings for AMD Versal NET EDAC for DDR controller. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> --- Changes in v4: Update the compatible align the example Enhance the description for rproc Changes in v2: - rename EDAC to memory controller - update the compatible name - Add remote proc handle - Read the data width from the registers - Remove the dwidth, rank and channel number the same is read from the RpMsg. .../amd,versal-net-ddrmc5-1.0.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/amd,versal-net-ddrmc5-1.0.yaml