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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2025 05:34:47.1381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d52c5a1-28be-4cd8-4541-08dd2e13d53a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5800 Add the commands for getting the DDRMC properties. Signed-off-by: Shubhrajyoti Datta --- (no changes since v1) drivers/cdx/controller/mc_cdx_pcol.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/cdx/controller/mc_cdx_pcol.h b/drivers/cdx/controller/mc_cdx_pcol.h index 832a44af963e..174270e148f3 100644 --- a/drivers/cdx/controller/mc_cdx_pcol.h +++ b/drivers/cdx/controller/mc_cdx_pcol.h @@ -302,6 +302,12 @@ #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_OFST 0 #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_LEN 4 +/* Number of registers */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_OFST 0 +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_LEN 4 +/* Number of registers for the DDR controller */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_REGISTER_VALUES_OFST 4 +#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_REGISTER_VALUES_LEN 4 /***********************************/ /* * MC_CMD_CDX_BUS_GET_DEVICE_CONFIG @@ -587,6 +593,16 @@ /* MC_CMD_CDX_DEVICE_CONTROL_SET_OUT msgresponse */ #define MC_CMD_CDX_DEVICE_CONTROL_SET_OUT_LEN 0 +/***********************************/ +/* MC_CMD_EDAC_GET_DDR_CONFIG + * Provides detailed configuration for the DDR controller of the given index. + */ +#define MC_CMD_EDAC_GET_DDR_CONFIG 0x3 + +/* MC_CMD_EDAC_GET_DDR_CONFIG_IN msgrequest */ +#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_OFST 0 +#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_LEN 4 + /***********************************/ /* * MC_CMD_CDX_DEVICE_CONTROL_GET