| Message ID | 20250213-wip-mca-updates-v2-12-3636547fe05f@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | AMD MCA interrupts rework | expand |
> From: Yazen Ghannam <yazen.ghannam@amd.com> > Sent: Friday, February 14, 2025 12:46 AM > To: x86@kernel.org; Luck, Tony <tony.luck@intel.com> > Cc: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org; > Smita.KoralahalliChannabasappa@amd.com; Yazen Ghannam > <yazen.ghannam@amd.com> > Subject: [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling > > AMD systems optionally support an MCA thresholding interrupt. The interrupt > should be used as another signal to trigger MCA polling. This is similar to how > the Intel Corrected Machine Check interrupt (CMCI) is handled. > > AMD MCA thresholding is managed using the MCA_MISC registers within an > MCA bank. The OS will need to modify the hardware error count field in order > to reset the threshold limit and rearm the interrupt. Management of the > MCA_MISC register should be done as a follow up to the basic MCA polling s/follow up/follow-up > flow. It should not be the main focus of the interrupt handler. > > Furthermore, future systems will have the ability to send an MCA > thresholding interrupt to the OS even when the OS does not manage the > feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. > > Call the common MCA polling function when handling the MCA thresholding > interrupt. This will allow the OS to find any valid errors whether or not the > MCA thresholding feature is OS-managed. Also, this allows the common MCA > polling options and kernel parameters to apply to AMD systems. > > Add a callback to the MCA polling function to check and reset any threshold > blocks that have reached their threshold limit. > > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
On Tue, Feb 18, 2025 at 06:42:52AM +0000, Zhuo, Qiuxu wrote: > > From: Yazen Ghannam <yazen.ghannam@amd.com> > > Sent: Friday, February 14, 2025 12:46 AM > > To: x86@kernel.org; Luck, Tony <tony.luck@intel.com> > > Cc: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org; > > Smita.KoralahalliChannabasappa@amd.com; Yazen Ghannam > > <yazen.ghannam@amd.com> > > Subject: [PATCH v2 12/16] x86/mce: Unify AMD THR handler with MCA Polling > > > > AMD systems optionally support an MCA thresholding interrupt. The interrupt > > should be used as another signal to trigger MCA polling. This is similar to how > > the Intel Corrected Machine Check interrupt (CMCI) is handled. > > > > AMD MCA thresholding is managed using the MCA_MISC registers within an > > MCA bank. The OS will need to modify the hardware error count field in order > > to reset the threshold limit and rearm the interrupt. Management of the > > MCA_MISC register should be done as a follow up to the basic MCA polling > > s/follow up/follow-up > Ack. > > flow. It should not be the main focus of the interrupt handler. > > > > Furthermore, future systems will have the ability to send an MCA > > thresholding interrupt to the OS even when the OS does not manage the > > feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. > > > > Call the common MCA polling function when handling the MCA thresholding > > interrupt. This will allow the OS to find any valid errors whether or not the > > MCA thresholding feature is OS-managed. Also, this allows the common MCA > > polling options and kernel parameters to apply to AMD systems. > > > > Add a callback to the MCA polling function to check and reset any threshold > > blocks that have reached their threshold limit. > > > > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> > > Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> > Thanks, Yazen
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index c6510415159f..5e491dbdeecc 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -54,6 +54,12 @@ static bool thresholding_irq_en; +struct mce_amd_cpu_data { + mce_banks_t thr_intr_banks; +}; + +static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data); + static const char * const th_names[] = { "load_store", "insn_fetch", @@ -559,6 +565,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, if (!b.interrupt_capable) goto done; + __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks); b.interrupt_enable = 1; if (!mce_flags.smca) { @@ -898,12 +905,7 @@ static void amd_deferred_error_interrupt(void) log_error_deferred(bank); } -static void log_error_thresholding(unsigned int bank, u64 misc) -{ - _log_error_deferred(bank, misc); -} - -static void log_and_reset_block(struct threshold_block *block) +static void reset_block(struct threshold_block *block) { struct thresh_restart tr; u32 low = 0, high = 0; @@ -917,23 +919,14 @@ static void log_and_reset_block(struct threshold_block *block) if (!(high & MASK_OVERFLOW_HI)) return; - /* Log the MCE which caused the threshold event. */ - log_error_thresholding(block->bank, ((u64)high << 32) | low); - - /* Reset threshold block after logging error. */ memset(&tr, 0, sizeof(tr)); tr.b = block; threshold_restart_bank(&tr); } -/* - * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt - * goes off when error_count reaches threshold_limit. - */ -static void amd_threshold_interrupt(void) +void amd_reset_thr_limit(unsigned int bank) { - struct threshold_bank **bp = this_cpu_read(threshold_banks), *thr_bank; - unsigned int bank, cpu = smp_processor_id(); + struct threshold_bank **bp = this_cpu_read(threshold_banks); struct threshold_block *block, *tmp; /* @@ -941,20 +934,20 @@ static void amd_threshold_interrupt(void) * handler is installed at boot time, but on a hotplug event the * interrupt might fire before the data has been initialized. */ - if (!bp) + if (!bp || !bp[bank]) return; - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { - if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) - continue; - - thr_bank = bp[bank]; - if (!thr_bank) - continue; + list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj) + reset_block(block); +} - list_for_each_entry_safe(block, tmp, &thr_bank->miscj, miscj) - log_and_reset_block(block); - } +/* + * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt + * goes off when error_count reaches threshold_limit. + */ +static void amd_threshold_interrupt(void) +{ + machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->thr_intr_banks); } /* diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 372e8b078dd5..b26eb576e413 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -809,6 +809,9 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) mce_log(&err); clear_it: + if (mce_flags.amd_threshold) + amd_reset_thr_limit(i); + /* * Clear state for this bank. */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index a4bae8c0cf4c..fe519acfafcf 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -268,6 +268,7 @@ void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m); void mce_threshold_create_device(unsigned int cpu); extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); +void amd_reset_thr_limit(unsigned int bank); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -298,6 +299,7 @@ void mce_smca_cpu_init(void); static inline void mce_threshold_create_device(unsigned int cpu) { } static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } +static inline void amd_reset_thr_limit(unsigned int bank) { } static inline void smca_extract_err_addr(struct mce *m) { } static inline void mce_smca_cpu_init(void) {} #endif
AMD systems optionally support an MCA thresholding interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how the Intel Corrected Machine Check interrupt (CMCI) is handled. AMD MCA thresholding is managed using the MCA_MISC registers within an MCA bank. The OS will need to modify the hardware error count field in order to reset the threshold limit and rearm the interrupt. Management of the MCA_MISC register should be done as a follow up to the basic MCA polling flow. It should not be the main focus of the interrupt handler. Furthermore, future systems will have the ability to send an MCA thresholding interrupt to the OS even when the OS does not manage the feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. Call the common MCA polling function when handling the MCA thresholding interrupt. This will allow the OS to find any valid errors whether or not the MCA thresholding feature is OS-managed. Also, this allows the common MCA polling options and kernel parameters to apply to AMD systems. Add a callback to the MCA polling function to check and reset any threshold blocks that have reached their threshold limit. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- Notes: Link: https://lore.kernel.org/r/20240523155641.2805411-7-yazen.ghannam@amd.com v1->v2: * Start collecting per-CPU items in a struct. * Keep and use mce_flags.amd_threshold. arch/x86/kernel/cpu/mce/amd.c | 49 ++++++++++++++++---------------------- arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 26 insertions(+), 28 deletions(-)