From patchwork Wed Mar 23 22:35:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Tobias Schandinat X-Patchwork-Id: 657331 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2NML00Y030830 for ; Wed, 23 Mar 2011 22:21:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932449Ab1CWWU4 (ORCPT ); Wed, 23 Mar 2011 18:20:56 -0400 Received: from mailout-de.gmx.net ([213.165.64.22]:33439 "HELO mailout-de.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1756794Ab1CWWUF (ORCPT ); Wed, 23 Mar 2011 18:20:05 -0400 Received: (qmail invoked by alias); 23 Mar 2011 22:20:04 -0000 Received: from dslb-088-065-185-053.pools.arcor-ip.net (EHLO localhost.localdomain) [88.65.185.53] by mail.gmx.net (mp016) with SMTP; 23 Mar 2011 23:20:04 +0100 X-Authenticated: #10250065 X-Provags-ID: V01U2FsdGVkX19xscsiA4Bx2XHiK0cJWry/2Lkihr8zISq4YpA8Ax dCrsU5MCJYXNjd From: Florian Tobias Schandinat To: linux-fbdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Florian Tobias Schandinat Subject: [PATCH 4/4] viafb: add clock source selection and PLL power management support Date: Wed, 23 Mar 2011 22:35:34 +0000 Message-Id: <1300919734-3931-5-git-send-email-FlorianSchandinat@gmx.de> X-Mailer: git-send-email 1.6.3.2 In-Reply-To: <1300919734-3931-1-git-send-email-FlorianSchandinat@gmx.de> References: <1300919734-3931-1-git-send-email-FlorianSchandinat@gmx.de> X-Y-GMX-Trusted: 0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 23 Mar 2011 22:21:00 +0000 (UTC) diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c index bd28e13..b38d3b4 100644 --- a/drivers/video/via/hw.c +++ b/drivers/video/via/hw.c @@ -1409,6 +1409,42 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) } +static void set_primary_pll_state(u8 state) +{ + u8 value; + + switch (state) { + case VIA_STATE_ON: + value = 0x20; + break; + case VIA_STATE_OFF: + value = 0x00; + break; + default: + return; + } + + via_write_reg_mask(VIASR, 0x2D, value, 0x30); +} + +static void set_secondary_pll_state(u8 state) +{ + u8 value; + + switch (state) { + case VIA_STATE_ON: + value = 0x08; + break; + case VIA_STATE_OFF: + value = 0x00; + break; + default: + return; + } + + via_write_reg_mask(VIASR, 0x2D, value, 0x08); +} + static u32 cle266_encode_pll(struct pll_config pll) { return (pll.multiplier << 8) @@ -1494,6 +1530,58 @@ static void vx855_set_secondary_pll(struct pll_config config) k800_set_secondary_pll_encoded(vx855_encode_pll(config)); } +enum via_clksrc { + VIA_CLKSRC_X1 = 0, + VIA_CLKSRC_TVX1, + VIA_CLKSRC_TVPLL, + VIA_CLKSRC_DVP1TVCLKR, + VIA_CLKSRC_CAP0, + VIA_CLKSRC_CAP1, +}; + +static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll) +{ + u8 data = 0; + + switch (source) { + case VIA_CLKSRC_X1: + data = 0x00; + break; + case VIA_CLKSRC_TVX1: + data = 0x02; + break; + case VIA_CLKSRC_TVPLL: + data = 0x04; /* 0x06 should be the same */ + break; + case VIA_CLKSRC_DVP1TVCLKR: + data = 0x0A; + break; + case VIA_CLKSRC_CAP0: + data = 0xC; + break; + case VIA_CLKSRC_CAP1: + data = 0x0E; + break; + } + + if (!use_pll) + data |= 1; + + return data; +} + +static void set_primary_clock_source(enum via_clksrc source, bool use_pll) +{ + u8 data = set_clock_source_common(source, use_pll) << 4; + via_write_reg_mask(VIACR, 0x6C, data, 0xF0); +} + +static void set_secondary_clock_source(enum via_clksrc source, bool use_pll) +{ + u8 data = set_clock_source_common(source, use_pll); + via_write_reg_mask(VIACR, 0x6C, data, 0x0F); +} + static inline u32 get_pll_internal_frequency(u32 ref_freq, struct pll_config pll) {