From patchwork Thu Mar 24 16:12:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Tobias Schandinat X-Patchwork-Id: 659071 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2OFw0mQ023017 for ; Thu, 24 Mar 2011 15:58:00 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757010Ab1CXP5b (ORCPT ); Thu, 24 Mar 2011 11:57:31 -0400 Received: from mailout-de.gmx.net ([213.165.64.22]:55450 "HELO mailout-de.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1757002Ab1CXP5a (ORCPT ); Thu, 24 Mar 2011 11:57:30 -0400 Received: (qmail invoked by alias); 24 Mar 2011 15:57:28 -0000 Received: from dslb-088-066-135-164.pools.arcor-ip.net (EHLO localhost.localdomain) [88.66.135.164] by mail.gmx.net (mp072) with SMTP; 24 Mar 2011 16:57:28 +0100 X-Authenticated: #10250065 X-Provags-ID: V01U2FsdGVkX1+kQgIB52ikkjcEXhJktY0duyALHYXaOpBVhCu7nx TiRwHiN8Af5AvC From: Florian Tobias Schandinat To: linux-fbdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Florian Tobias Schandinat Subject: [PATCH 1/3] viafb: add primary/secondary clock on/off switches Date: Thu, 24 Mar 2011 16:12:58 +0000 Message-Id: <1300983180-7343-2-git-send-email-FlorianSchandinat@gmx.de> X-Mailer: git-send-email 1.6.3.2 In-Reply-To: <1300983180-7343-1-git-send-email-FlorianSchandinat@gmx.de> References: <1300983180-7343-1-git-send-email-FlorianSchandinat@gmx.de> X-Y-GMX-Trusted: 0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 24 Mar 2011 15:58:00 +0000 (UTC) diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c index b38d3b4..712348d 100644 --- a/drivers/video/via/hw.c +++ b/drivers/video/via/hw.c @@ -1409,6 +1409,42 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) } +static void set_primary_clock_state(u8 state) +{ + u8 value; + + switch (state) { + case VIA_STATE_ON: + value = 0x20; + break; + case VIA_STATE_OFF: + value = 0x00; + break; + default: + return; + } + + via_write_reg_mask(VIASR, 0x1B, value, 0x30); +} + +static void set_secondary_clock_state(u8 state) +{ + u8 value; + + switch (state) { + case VIA_STATE_ON: + value = 0x80; + break; + case VIA_STATE_OFF: + value = 0x00; + break; + default: + return; + } + + via_write_reg_mask(VIASR, 0x1B, value, 0xC0); +} + static void set_primary_pll_state(u8 state) { u8 value; @@ -1442,7 +1478,7 @@ static void set_secondary_pll_state(u8 state) return; } - via_write_reg_mask(VIASR, 0x2D, value, 0x08); + via_write_reg_mask(VIASR, 0x2D, value, 0x0C); } static u32 cle266_encode_pll(struct pll_config pll)