From patchwork Tue Apr 19 09:22:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 717321 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3J9Mbdo019830 for ; Tue, 19 Apr 2011 09:22:42 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753487Ab1DSJWi (ORCPT ); Tue, 19 Apr 2011 05:22:38 -0400 Received: from na3sys009aog117.obsmtp.com ([74.125.149.242]:46194 "EHLO na3sys009aog117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753051Ab1DSJWg (ORCPT ); Tue, 19 Apr 2011 05:22:36 -0400 Received: from mail-ew0-f51.google.com ([209.85.215.51]) (using TLSv1) by na3sys009aob117.postini.com ([74.125.148.12]) with SMTP ID DSNKTa1UW6RIA4JeLfijy+x/vI7ALCFSQ/v+@postini.com; Tue, 19 Apr 2011 02:22:36 PDT Received: by mail-ew0-f51.google.com with SMTP id 6so1740441ewy.38 for ; Tue, 19 Apr 2011 02:22:34 -0700 (PDT) Received: by 10.14.10.129 with SMTP id 1mr2044712eev.150.1303204954560; Tue, 19 Apr 2011 02:22:34 -0700 (PDT) Received: from deskari (a62-248-131-233.elisa-laajakaista.fi [62.248.131.233]) by mx.google.com with ESMTPS id m55sm4672311eei.8.2011.04.19.02.22.32 (version=SSLv3 cipher=OTHER); Tue, 19 Apr 2011 02:22:33 -0700 (PDT) From: Tomi Valkeinen To: linux-omap@vger.kernel.org, linux-fbdev@vger.kernel.org Cc: Tomi Valkeinen Subject: [PATCH 01/19] OMAP: DSS2: DSI: Add lane override functions Date: Tue, 19 Apr 2011 12:22:04 +0300 Message-Id: <1303204942-25450-2-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1303204942-25450-1-git-send-email-tomi.valkeinen@ti.com> References: <1303204942-25450-1-git-send-email-tomi.valkeinen@ti.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 19 Apr 2011 09:22:42 +0000 (UTC) DSI_DSIPHY_CFG10 register can be used to override DSI lane state. Add functions to configure and enable the override, and to disable the override. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 58 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 58 insertions(+), 0 deletions(-) diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 2666b6b..d245c5c 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -90,6 +90,7 @@ struct dsi_reg { u16 idx; }; #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) +#define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) /* DSI_PLL_CTRL_SCP */ @@ -208,6 +209,15 @@ enum dsi_vc_mode { DSI_VC_MODE_VP, }; +enum dsi_lane { + DSI_CLK_P = 1 << 0, + DSI_CLK_N = 1 << 1, + DSI_DATA1_P = 1 << 2, + DSI_DATA1_N = 1 << 3, + DSI_DATA2_P = 1 << 4, + DSI_DATA2_N = 1 << 5, +}; + struct dsi_update_region { u16 x, y, w, h; struct omap_dss_device *device; @@ -1863,6 +1873,54 @@ static void dsi_complexio_timings(void) dsi_write_reg(DSI_DSIPHY_CFG2, r); } +static void dsi_enable_lane_override(struct omap_dss_device *dssdev, + enum dsi_lane lanes) +{ + int clk_lane = dssdev->phy.dsi.clk_lane; + int data1_lane = dssdev->phy.dsi.data1_lane; + int data2_lane = dssdev->phy.dsi.data2_lane; + int clk_pol = dssdev->phy.dsi.clk_pol; + int data1_pol = dssdev->phy.dsi.data1_pol; + int data2_pol = dssdev->phy.dsi.data2_pol; + + u32 l = 0; + + if (lanes & DSI_CLK_P) + l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1)); + if (lanes & DSI_CLK_N) + l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0)); + + if (lanes & DSI_DATA1_P) + l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1)); + if (lanes & DSI_DATA1_N) + l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0)); + + if (lanes & DSI_DATA2_P) + l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1)); + if (lanes & DSI_DATA2_N) + l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0)); + + /* + * Bits in REGLPTXSCPDAT4TO0DXDY: + * 17: DY0 18: DX0 + * 19: DY1 20: DX1 + * 21: DY2 22: DX2 + */ + + /* Set the lane override configuration */ + REG_FLD_MOD(DSI_DSIPHY_CFG10, l, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ + + /* Enable lane override */ + REG_FLD_MOD(DSI_DSIPHY_CFG10, 1, 27, 27); /* ENLPTXSCPDAT */ +} + +static void dsi_disable_lane_override(void) +{ + /* Disable lane override */ + REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ + /* Reset the lane override configuration */ + REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ +} static int dsi_complexio_init(struct omap_dss_device *dssdev) {