From patchwork Wed Aug 8 03:54:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 1292351 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 82AE2DF223 for ; Wed, 8 Aug 2012 03:54:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756245Ab2HHDyi (ORCPT ); Tue, 7 Aug 2012 23:54:38 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:48841 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756127Ab2HHDyh (ORCPT ); Tue, 7 Aug 2012 23:54:37 -0400 Received: by mail-pb0-f46.google.com with SMTP id rr13so760482pbb.19 for ; Tue, 07 Aug 2012 20:54:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=wg1BpG4EtWSE2TRCt7AZvukprHCZatbmL7RWKv7i0kc=; b=WDQuSNXrWaByEpe0SlHW94oyjjlAq0yteJOAZ2t+zsV9iKm/HUcKY5d9YxfOrSksf6 Q5APWbxewmYOOsq5MN7h1GzMyoc6w2dp/VFqY8KE/m8O0We0myhqLLl0eeHhMVTTLX1q so9XPY6uwb9J4iL0eJ4+ihWWqxrDmtIq00gdg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=wg1BpG4EtWSE2TRCt7AZvukprHCZatbmL7RWKv7i0kc=; b=DV204jVxExmVIwnDmmsUgHR++5XT6pnYBEHQm6/hGUpVeK7wHQQY6yu6BD0uNWCCxr AXczVgxrQzZQh6q6YdZOgAw4zAO7+Gp7l5rd99INJD2PD7LZZgIyBcB6vxNvtkqzP/DA V5Ub2BDetMHmUjLvFM6m89AChbXOxpdXvSWMsAw+ak4Ag95kFkQY6wkZF6+86gYx9bn5 50LDjb2Lik9JOdVhHqq5TPYjkVYGBXC0XkUZPD+ZkTw1r7bgmf1cTMH/0QKgdCgpUyzh dVnZ5laEw8l/ncqGCVs+Z8pdrt9/bRnXCKLU97V7KAhghWptyWT8QyIpPEgE4i3sbcpq /lGA== Received: by 10.68.221.106 with SMTP id qd10mr33303923pbc.42.1344398077205; Tue, 07 Aug 2012 20:54:37 -0700 (PDT) Received: from anush.mtv.corp.google.com (anush.mtv.corp.google.com [172.22.73.28]) by mx.google.com with ESMTPS id hx9sm12461756pbc.68.2012.08.07.20.54.36 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 07 Aug 2012 20:54:36 -0700 (PDT) From: Sean Paul To: jg1.han@samsung.com, linux-fbdev@vger.kernel.org Cc: Sean Paul Subject: [PATCH 03/10] video: exynos_dp: Clean up SW link training Date: Tue, 7 Aug 2012 20:54:17 -0700 Message-Id: <1344398064-13563-4-git-send-email-seanpaul@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1344398064-13563-1-git-send-email-seanpaul@chromium.org> References: <1344398064-13563-1-git-send-email-seanpaul@chromium.org> X-Gm-Message-State: ALoCoQmjYx42SnZGO0118AWHTUhAaDjwi+s4/1HRG0w3A609Dl+zGsT4wM503thR2vMRR5gdyGcW Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Clean up some of the SW training code to make it more clear and reduce duplicate code. Signed-off-by: Sean Paul Reviewed-by: Mandeep Singh Baines --- drivers/video/exynos/exynos_dp_core.c | 180 ++++++++++++--------------------- 1 files changed, 67 insertions(+), 113 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index 1836e33..3deded2 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -260,10 +260,8 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static int exynos_dp_link_start(struct exynos_dp_device *dp) { - int ret; - u8 buf[5]; - int lane; - int lane_count; + int ret, lane, lane_count; + u8 buf[4]; lane_count = dp->link_train.lane_count; @@ -286,8 +284,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) /* Setup RX configuration */ buf[0] = dp->link_train.link_rate; buf[1] = dp->link_train.lane_count; - ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, - 2, buf); + ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf); if (ret) return ret; @@ -300,16 +297,15 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) exynos_dp_set_training_pattern(dp, TRAINING_PTN1); /* Set RX training pattern */ - buf[0] = DPCD_SCRAMBLING_DISABLED | - DPCD_TRAINING_PATTERN_1; - exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]); + ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, + DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1); + if (ret) + return ret; for (lane = 0; lane < lane_count; lane++) buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0; - ret = exynos_dp_write_bytes_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET, + ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, buf); if (ret) return ret; @@ -484,67 +480,32 @@ static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp, static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { - int ret; - u8 data; - u8 link_status[6]; - int lane; - int lane_count; - u8 buf[5]; - - u8 adjust_request[2]; - u8 voltage_swing; - u8 pre_emphasis; - u8 training_lane; + int ret, lane, lane_count; + u8 voltage_swing, pre_emphasis, training_lane, link_status[6]; + u8 *adjust_request; usleep_range(100, 101); - ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, - 6, link_status); + ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6, + link_status); if (ret) return ret; lane_count = dp->link_train.lane_count; + adjust_request = link_status + 4; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); - adjust_request[0] = link_status[4]; - adjust_request[1] = link_status[5]; - - exynos_dp_get_adjust_train(dp, adjust_request); - - buf[0] = DPCD_SCRAMBLING_DISABLED | - DPCD_TRAINING_PATTERN_2; ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - buf[0]); + DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); if (ret) return ret; - for (lane = 0; lane < lane_count; lane++) { - exynos_dp_set_lane_link_training(dp, - dp->link_train.training_lane[lane], - lane); - buf[lane] = dp->link_train.training_lane[lane]; - ret = exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET + lane, - buf[lane]); - if (ret) - return ret; - } dp->link_train.lt_state = EQUALIZER_TRAINING; } else { - exynos_dp_read_byte_from_dpcd(dp, - DPCD_ADDR_ADJUST_REQUEST_LANE0_1, - &data); - adjust_request[0] = data; - - exynos_dp_read_byte_from_dpcd(dp, - DPCD_ADDR_ADJUST_REQUEST_LANE2_3, - &data); - adjust_request[1] = data; - for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); @@ -560,36 +521,31 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) { exynos_dp_reduce_link_rate(dp); - } else { - exynos_dp_get_adjust_train(dp, adjust_request); - - for (lane = 0; lane < lane_count; lane++) { - exynos_dp_set_lane_link_training(dp, - dp->link_train.training_lane[lane], - lane); - buf[lane] = dp->link_train.training_lane[lane]; - ret = exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET + lane, - buf[lane]); - if (ret) - return ret; - } + return ret; } } + exynos_dp_get_adjust_train(dp, adjust_request); + + for (lane = 0; lane < lane_count; lane++) { + exynos_dp_set_lane_link_training(dp, + dp->link_train.training_lane[lane], lane); + ret = exynos_dp_write_byte_to_dpcd(dp, + DPCD_ADDR_TRAINING_LANE0_SET + lane, + dp->link_train.training_lane[lane]); + if (ret) + return ret; + } + return ret; } static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) { - int ret; + int ret, lane, lane_count; u8 link_status[6]; - int lane; - int lane_count; - u8 buf[5]; u32 reg; - - u8 adjust_request[2]; + u8 *adjust_request; usleep_range(400, 401); @@ -597,55 +553,53 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) 6, link_status); if (ret) return ret; + + adjust_request = link_status + 4; lane_count = dp->link_train.lane_count; - if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { - adjust_request[0] = link_status[4]; - adjust_request[1] = link_status[5]; + if (exynos_dp_clock_recovery_ok(link_status, lane_count)) { + exynos_dp_reduce_link_rate(dp); + return ret; + } + if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) { + /* traing pattern Set to Normal */ + exynos_dp_training_pattern_dis(dp); - if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) { - /* traing pattern Set to Normal */ - exynos_dp_training_pattern_dis(dp); + dev_info(dp->dev, "Link Training success!\n"); - dev_info(dp->dev, "Link Training success!\n"); + exynos_dp_get_link_bandwidth(dp, ®); + dp->link_train.link_rate = reg; + dev_dbg(dp->dev, "final bandwidth = %.2x\n", + dp->link_train.link_rate); - exynos_dp_get_link_bandwidth(dp, ®); - dp->link_train.link_rate = reg; - dev_dbg(dp->dev, "final bandwidth = %.2x\n", - dp->link_train.link_rate); + exynos_dp_get_lane_count(dp, ®); + dp->link_train.lane_count = reg; + dev_dbg(dp->dev, "final lane count = %.2x\n", + dp->link_train.lane_count); + /* set enhanced mode if available */ + exynos_dp_set_enhanced_mode(dp); - exynos_dp_get_lane_count(dp, ®); - dp->link_train.lane_count = reg; - dev_dbg(dp->dev, "final lane count = %.2x\n", - dp->link_train.lane_count); - /* set enhanced mode if available */ - exynos_dp_set_enhanced_mode(dp); + dp->link_train.lt_state = FINISHED; + } else { + /* not all locked */ + dp->link_train.eq_loop++; - dp->link_train.lt_state = FINISHED; + if (dp->link_train.eq_loop > MAX_EQ_LOOP) { + exynos_dp_reduce_link_rate(dp); } else { - /* not all locked */ - dp->link_train.eq_loop++; - - if (dp->link_train.eq_loop > MAX_EQ_LOOP) { - exynos_dp_reduce_link_rate(dp); - } else { - exynos_dp_get_adjust_train(dp, adjust_request); - - for (lane = 0; lane < lane_count; lane++) { - exynos_dp_set_lane_link_training(dp, - dp->link_train.training_lane[lane], - lane); - buf[lane] = dp->link_train.training_lane[lane]; - ret = exynos_dp_write_byte_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET + lane, - buf[lane]); - if (ret) - return ret; - } + exynos_dp_get_adjust_train(dp, adjust_request); + + for (lane = 0; lane < lane_count; lane++) { + exynos_dp_set_lane_link_training(dp, + dp->link_train.training_lane[lane], + lane); + ret = exynos_dp_write_byte_to_dpcd(dp, + DPCD_ADDR_TRAINING_LANE0_SET + lane, + dp->link_train.training_lane[lane]); + if (ret) + return ret; } } - } else { - exynos_dp_reduce_link_rate(dp); } return ret;