From patchwork Wed Aug 8 03:54:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 1292361 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id C6887DF223 for ; Wed, 8 Aug 2012 03:54:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754972Ab2HHDyj (ORCPT ); Tue, 7 Aug 2012 23:54:39 -0400 Received: from mail-pb0-f46.google.com ([209.85.160.46]:48841 "EHLO mail-pb0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756127Ab2HHDyi (ORCPT ); Tue, 7 Aug 2012 23:54:38 -0400 Received: by mail-pb0-f46.google.com with SMTP id rr13so760482pbb.19 for ; Tue, 07 Aug 2012 20:54:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=YpcGPX9N7ym4LUKcp7Uatl8E4DwsFLTDhLJSzeBNR9Y=; b=jsGqE7RiuESNBYXJr398O5BEs5g8x+5vq/YXGz1Gw8kBbuPKgUNtZj/h5z+Dqys3ec Ikh52VHX1KpKyE0dXfnWuRqfHSn8vIqt0CMdaQhAFAeqsGnoPLnqEnC03UgcDEwmjYRd BccYrntnWzh7tUlyGpm2h1NjMDSPNrQKheDXI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=YpcGPX9N7ym4LUKcp7Uatl8E4DwsFLTDhLJSzeBNR9Y=; b=EZBvGpJXoPUrQH9W00s/zTRUd2b8aURek472PyEAtGGTeOARjgzqMTeFm5Eb8Pm73O YYsezgJFs+Z3tR/YP/fDLQtNYFJJTNMlkSejJchq9b4qKf+j7eGZJ/XQVvZ/gKWgrO4i k8f0AkqIr56ZOmzci5jRXmU/SWTr45OHIU/ZVFXPxrm3lk2Wc2e0iS3EDSHiBXDQitPC wQDNQz/sTersTP6hbQALDC5nIruFpiqZA4bJsIL5+AC4wuQm/lbQTYTBpgeR+eflPFuF dwSccKYPN2Pmro7mUEb3UsFl1UZgosph9bVG9Nd/xb69uIk1zrbng2INL2bZFdM/+T6h Oh8g== Received: by 10.68.200.162 with SMTP id jt2mr32673395pbc.54.1344398078228; Tue, 07 Aug 2012 20:54:38 -0700 (PDT) Received: from anush.mtv.corp.google.com (anush.mtv.corp.google.com [172.22.73.28]) by mx.google.com with ESMTPS id hx9sm12461756pbc.68.2012.08.07.20.54.37 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 07 Aug 2012 20:54:37 -0700 (PDT) From: Sean Paul To: jg1.han@samsung.com, linux-fbdev@vger.kernel.org Cc: Sean Paul Subject: [PATCH 04/10] video: exynos_dp: Get pll lock before pattern set Date: Tue, 7 Aug 2012 20:54:18 -0700 Message-Id: <1344398064-13563-5-git-send-email-seanpaul@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1344398064-13563-1-git-send-email-seanpaul@chromium.org> References: <1344398064-13563-1-git-send-email-seanpaul@chromium.org> X-Gm-Message-State: ALoCoQnTkeXgp9z7I88eiWHdPZd0gyBBHZpKNU6dmtZzxfHfABKUoXtpzSHh7QMel3UVSG8HcSqe Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org According to the exynos datasheet (Figure 49-10), we should wait for PLL lock before programming the training pattern when doing software eDP link training. Signed-off-by: Sean Paul Reviewed-by: Mandeep Singh Baines --- drivers/video/exynos/exynos_dp_core.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index 3deded2..207bd7e 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -23,6 +23,8 @@ #include "exynos_dp_core.h" +#define PLL_MAX_TRIES 100 + static int exynos_dp_init_dp(struct exynos_dp_device *dp) { exynos_dp_reset(dp); @@ -260,7 +262,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static int exynos_dp_link_start(struct exynos_dp_device *dp) { - int ret, lane, lane_count; + int ret, lane, lane_count, pll_tries; u8 buf[4]; lane_count = dp->link_train.lane_count; @@ -293,6 +295,16 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); + /* Wait for PLL lock */ + pll_tries = 0; + while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (pll_tries == PLL_MAX_TRIES) + return -ETIMEDOUT; + + pll_tries++; + udelay(100); + } + /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1);