From patchwork Tue Aug 21 06:09:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1352371 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 6371C40B05 for ; Tue, 21 Aug 2012 06:10:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753540Ab2HUGKh (ORCPT ); Tue, 21 Aug 2012 02:10:37 -0400 Received: from na3sys009aog121.obsmtp.com ([74.125.149.145]:58302 "EHLO na3sys009aog121.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753476Ab2HUGKg (ORCPT ); Tue, 21 Aug 2012 02:10:36 -0400 Received: from mail-lpp01m010-f53.google.com ([209.85.215.53]) (using TLSv1) by na3sys009aob121.postini.com ([74.125.148.12]) with SMTP ID DSNKUDMmWrHE0HP88ux1yhV1msfCbwxLho0N@postini.com; Mon, 20 Aug 2012 23:10:35 PDT Received: by lahc1 with SMTP id c1so3896768lah.12 for ; Mon, 20 Aug 2012 23:10:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=7v5WBiG2Cma9xyRU4p/g7sq0dwzwvRRLBGxrUAiKfvw=; b=N/iTlv0qB81lxmAxzTIDGUKewC72CnOgJgNl8ZVfkwV3OqtR3gD7zFFnYyTMRai6P0 QT9vK3G3hQHBIF+lqtfW2LoNhQ40gClqRU70EHbrwfHjI8XrHoI7HXVZXXA6p8UoDPR6 xzPOUscZpUSRjAdq8smiABcwIHhghwl9GZkY3LL7tkFjXRRAdpinC+yVstLBynAPBBJB LpTfPUFgVK903lascUOhAJeF79qdwCv76Rt5zNLUqhcuxzccfe/EE17OVCDB9LywYeJs /xcd2GfWJFMEsILM0cGPO1iQL5W3UKfo02oqQkIBRKZM4kPZyUb3vrit4GiRQ9fswSz1 Yeyw== Received: by 10.152.144.9 with SMTP id si9mr16647641lab.4.1345529432616; Mon, 20 Aug 2012 23:10:32 -0700 (PDT) Received: from localhost.localdomain (a91-156-160-115.elisa-laajakaista.fi. [91.156.160.115]) by mx.google.com with ESMTPS id ta2sm562054lab.15.2012.08.20.23.10.31 (version=SSLv3 cipher=OTHER); Mon, 20 Aug 2012 23:10:31 -0700 (PDT) From: Tomi Valkeinen To: Florian Tobias Schandinat Cc: linux-fbdev@vger.kernel.org, linux-omap@vger.kernel.org, Tomi Valkeinen Subject: [PATCH 1/2] OMAPDSS: Fix SDI PLL locking Date: Tue, 21 Aug 2012 09:09:47 +0300 Message-Id: <1345529388-3509-2-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1345529388-3509-1-git-send-email-tomi.valkeinen@ti.com> References: <1345529388-3509-1-git-send-email-tomi.valkeinen@ti.com> X-Gm-Message-State: ALoCoQkftqUswk7WghoDt8WkIrrsp5tv3yLnuDsOAXT0+Fxr1cIGs0x7YxZfg5ue027WPS4+hePw Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Commit f476ae9dab3234532d41d36beb4ba7be838fa786 (OMAPDSS: APPLY: Remove DISPC writes to manager's lcd parameters in interface) broke the SDI output, as it causes the SDI PLL locking to fail. LCLK and PCLK divisors are located in shadow registers, and we normally write them to DISPC registers when enabling the output. However, SDI uses pck-free as source clock for its PLL, and pck-free is affected by the divisors. And as we need the PLL before enabling the output, we need to write the divisors early. It seems just writing to the DISPC register is enough, and we don't need to care about the shadow register mechanism for pck-free. The exact reason for this is unknown. Signed-off-by: Tomi Valkeinen Reported-by: Aaro Koskinen --- drivers/video/omap2/dss/sdi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c index 5d31699..f43bfe1 100644 --- a/drivers/video/omap2/dss/sdi.c +++ b/drivers/video/omap2/dss/sdi.c @@ -105,6 +105,20 @@ int omapdss_sdi_display_enable(struct omap_dss_device *dssdev) sdi_config_lcd_manager(dssdev); + /* + * LCLK and PCLK divisors are located in shadow registers, and we + * normally write them to DISPC registers when enabling the output. + * However, SDI uses pck-free as source clock for its PLL, and pck-free + * is affected by the divisors. And as we need the PLL before enabling + * the output, we need to write the divisors early. + * + * It seems just writing to the DISPC register is enough, and we don't + * need to care about the shadow register mechanism for pck-free. The + * exact reason for this is unknown. + */ + dispc_mgr_set_clock_div(dssdev->manager->id, + &sdi.mgr_config.clock_info); + dss_sdi_init(dssdev->phy.sdi.datapairs); r = dss_sdi_enable(); if (r)