From patchwork Wed Oct 17 11:20:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1605181 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 3FA9E3FE36 for ; Wed, 17 Oct 2012 11:20:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756645Ab2JQLUw (ORCPT ); Wed, 17 Oct 2012 07:20:52 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59187 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756656Ab2JQLUu (ORCPT ); Wed, 17 Oct 2012 07:20:50 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9HBKoqV009891; Wed, 17 Oct 2012 06:20:50 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9HBKoLn031553; Wed, 17 Oct 2012 06:20:50 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Wed, 17 Oct 2012 06:20:50 -0500 Received: from deskari.tieu.ti.com (h64-2.vpn.ti.com [172.24.64.2]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9HBKbNk030439; Wed, 17 Oct 2012 06:20:49 -0500 From: Tomi Valkeinen To: , , CC: Tomi Valkeinen Subject: [PATCH 7/9] OMAPDSS: DISPC: cleanup lcd and digit enable Date: Wed, 17 Oct 2012 14:20:33 +0300 Message-ID: <1350472835-28727-8-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1350472835-28727-1-git-send-email-tomi.valkeinen@ti.com> References: <1350472835-28727-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org dispc.c's functions to enable LCD and DIGIT outputs can be cleaned up a bit by using common functions to set the enable bit and to check if the output is enabled. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 9f0ce18..492740e 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2591,13 +2591,18 @@ static void dispc_disable_isr(void *data, u32 mask) complete(compl); } -static void _enable_lcd_out(enum omap_channel channel, bool enable) +static void _enable_mgr_out(enum omap_channel channel, bool enable) { mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); /* flush posted write */ mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); } +bool dispc_mgr_is_enabled(enum omap_channel channel) +{ + return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); +} + static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) { struct completion frame_done_completion; @@ -2608,7 +2613,7 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) /* When we disable LCD output, we need to wait until frame is done. * Otherwise the DSS is still working, and turning off the clocks * prevents DSS from going to OFF mode */ - is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); + is_on = dispc_mgr_is_enabled(channel); irq = mgr_desc[channel].framedone_irq; @@ -2622,7 +2627,7 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) DSSERR("failed to register FRAMEDONE isr\n"); } - _enable_lcd_out(channel, enable); + _enable_mgr_out(channel, enable); if (!enable && is_on) { if (!wait_for_completion_timeout(&frame_done_completion, @@ -2637,13 +2642,6 @@ static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) } } -static void _enable_digit_out(bool enable) -{ - REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1); - /* flush posted write */ - dispc_read_reg(DISPC_CONTROL); -} - static void dispc_mgr_enable_digit_out(bool enable) { struct completion frame_done_completion; @@ -2652,7 +2650,7 @@ static void dispc_mgr_enable_digit_out(bool enable) u32 irq_mask; int num_irqs; - if (REG_GET(DISPC_CONTROL, 1, 1) == enable) + if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == enable) return; src = dss_get_hdmi_venc_clk_source(); @@ -2689,7 +2687,7 @@ static void dispc_mgr_enable_digit_out(bool enable) if (r) DSSERR("failed to register %x isr\n", irq_mask); - _enable_digit_out(enable); + _enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, enable); for (i = 0; i < num_irqs; ++i) { if (!wait_for_completion_timeout(&frame_done_completion, @@ -2713,11 +2711,6 @@ static void dispc_mgr_enable_digit_out(bool enable) } } -bool dispc_mgr_is_enabled(enum omap_channel channel) -{ - return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); -} - void dispc_mgr_enable(enum omap_channel channel, bool enable) { if (dss_mgr_is_lcd(channel))