From patchwork Wed Oct 24 06:58:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhou Zhu X-Patchwork-Id: 1636021 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E2CEBDF2AB for ; Wed, 24 Oct 2012 06:54:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933722Ab2JXGyh (ORCPT ); Wed, 24 Oct 2012 02:54:37 -0400 Received: from na3sys009aog135.obsmtp.com ([74.125.149.84]:60189 "EHLO na3sys009aog135.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933727Ab2JXGyf (ORCPT ); Wed, 24 Oct 2012 02:54:35 -0400 Received: from MSI-MTA.marvell.com ([65.219.4.132]) (using TLSv1) by na3sys009aob135.postini.com ([74.125.148.12]) with SMTP ID DSNKUIeQqDuvA0vIDIQO4XOCmgBUdJLcYbgq@postini.com; Tue, 23 Oct 2012 23:54:35 PDT Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 23 Oct 2012 23:54:14 -0700 Received: from localhost (unknown [10.38.36.52]) by maili.marvell.com (Postfix) with ESMTP id 139BD4E510; Tue, 23 Oct 2012 23:54:14 -0700 (PDT) From: Zhou Zhu To: , , Cc: , Zhou Zhu Subject: [PATCHv4 7/9] ARM: mmp: add lcd clock support Date: Wed, 24 Oct 2012 14:58:38 +0800 Message-Id: <1351061918-6522-1-git-send-email-zzhu3@marvell.com> X-Mailer: git-send-email 1.7.0.4 X-OriginalArrivalTime: 24 Oct 2012 06:54:14.0248 (UTC) FILETIME=[60F48680:01CDB1B4] Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org added lcd clock support Signed-off-by: Zhou Zhu --- arch/arm/mach-mmp/pxa910.c | 32 +++++++++++++++++++++++++++++++- 1 files changed, 31 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 7d7c43b..78c6eb8 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -82,6 +82,35 @@ void __init pxa910_init_irq(void) icu_init_irq(); } +static void lcd_clk_enable(struct clk *clk) +{ + writel_relaxed(clk->enable_val, clk->clk_rst); +} +static void lcd_clk_disable(struct clk *clk) +{ + u32 tmp = readl_relaxed(clk->clk_rst); + tmp &= ~0x38; /* release from reset to keep register setting */ + writel_relaxed(tmp, clk->clk_rst); +} + +static int lcd_clk_setrate(struct clk *clk, unsigned long val) +{ + writel_relaxed(val, clk->clk_rst); + return 0; +} +static unsigned long lcd_clk_getrate(struct clk *clk) +{ + unsigned long rate = clk->rate; + return rate; +} + +struct clkops lcd_pn1_clk_ops = { + .enable = lcd_clk_enable, + .disable = lcd_clk_disable, + .setrate = lcd_clk_setrate, + .getrate = lcd_clk_getrate, +}; + /* APB peripheral clocks */ static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); @@ -93,7 +122,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000); static APBC_CLK(rtc, PXA910_RTC, 8, 32768); - +static APMU_CLK_OPS(lcd, LCD, 0x003f, 312000000, &lcd_pn1_clk_ops); static APMU_CLK(nand, NAND, 0x19b, 156000000); static APMU_CLK(u2o, USB, 0x1b, 480000000); @@ -111,6 +140,7 @@ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), + INIT_CLKREG(&clk_lcd, NULL, "LCDCLK"), }; static int __init pxa910_init(void)