From patchwork Wed Oct 24 09:29:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1636871 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id CB3A33FC36 for ; Wed, 24 Oct 2012 09:30:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934498Ab2JXJau (ORCPT ); Wed, 24 Oct 2012 05:30:50 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59711 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934475Ab2JXJ3l (ORCPT ); Wed, 24 Oct 2012 05:29:41 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9O9Teet022800; Wed, 24 Oct 2012 04:29:40 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9O9Te5i018918; Wed, 24 Oct 2012 04:29:40 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Wed, 24 Oct 2012 04:29:40 -0500 Received: from deskari.tieu.ti.com (h64-3.vpn.ti.com [172.24.64.3]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9O9TOBK028560; Wed, 24 Oct 2012 04:29:39 -0500 From: Tomi Valkeinen To: , , CC: Tomi Valkeinen Subject: [PATCH 10/20] OMAPDSS: DISPC: Add IRQ enable/status helpers Date: Wed, 24 Oct 2012 12:29:01 +0300 Message-ID: <1351070951-18616-11-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1351070951-18616-1-git-send-email-tomi.valkeinen@ti.com> References: <1351070951-18616-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org DISPC irqs need to be handled from the compat layer and also in the future by the omapdrm. To make this possible, this patchs adds a set of helper functions, so that the irqs can be managed without direct register reads/writes. The following functions are added, and all the current direct reg reads/writes are changed to use these. u32 dispc_read_irqstatus(void); void dispc_clear_irqstatus(u32 mask); u32 dispc_read_irqenable(void); void dispc_write_irqenable(u32 mask); Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 44 ++++++++++++++++++++++++++++----------- drivers/video/omap2/dss/dss.h | 4 ++++ 2 files changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 3fd60ce..d294873 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -497,7 +497,7 @@ static void dispc_restore_context(void) if (dss_has_feature(FEAT_MGR_LCD3)) RR(CONTROL3); /* clear spurious SYNC_LOST_DIGIT interrupts */ - dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); + dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); /* * enable last so IRQs won't trigger before @@ -3627,11 +3627,35 @@ int dispc_mgr_get_clock_div(enum omap_channel channel, return 0; } +u32 dispc_read_irqstatus(void) +{ + return dispc_read_reg(DISPC_IRQSTATUS); +} + +void dispc_clear_irqstatus(u32 mask) +{ + dispc_write_reg(DISPC_IRQSTATUS, mask); +} + +u32 dispc_read_irqenable(void) +{ + return dispc_read_reg(DISPC_IRQENABLE); +} + +void dispc_write_irqenable(u32 mask) +{ + u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); + + /* clear the irqstatus for newly enabled irqs */ + dispc_clear_irqstatus((mask ^ old_mask) & mask); + + dispc_write_reg(DISPC_IRQENABLE, mask); +} + /* dispc.irq_lock has to be locked by the caller */ static void _omap_dispc_set_irqs(void) { u32 mask; - u32 old_mask; int i; struct omap_dispc_isr_data *isr_data; @@ -3646,11 +3670,7 @@ static void _omap_dispc_set_irqs(void) mask |= isr_data->mask; } - old_mask = dispc_read_reg(DISPC_IRQENABLE); - /* clear the irqstatus for newly enabled irqs */ - dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); - - dispc_write_reg(DISPC_IRQENABLE, mask); + dispc_write_irqenable(mask); } int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) @@ -3777,8 +3797,8 @@ static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) spin_lock(&dispc.irq_lock); - irqstatus = dispc_read_reg(DISPC_IRQSTATUS); - irqenable = dispc_read_reg(DISPC_IRQENABLE); + irqstatus = dispc_read_irqstatus(); + irqenable = dispc_read_irqenable(); /* IRQ is not for us */ if (!(irqstatus & irqenable)) { @@ -3797,9 +3817,9 @@ static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) /* Ack the interrupt. Do it here before clocks are possibly turned * off */ - dispc_write_reg(DISPC_IRQSTATUS, irqstatus); + dispc_clear_irqstatus(irqstatus); /* flush posted write */ - dispc_read_reg(DISPC_IRQSTATUS); + dispc_read_irqstatus(); /* make a copy and unlock, so that isrs can unregister * themselves */ @@ -4008,7 +4028,7 @@ static void _omap_dispc_initialize_irq(void) /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, * so clear it */ - dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS)); + dispc_clear_irqstatus(dispc_read_irqstatus()); _omap_dispc_set_irqs(); diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index be7678c..8bf9047 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -398,6 +398,10 @@ void dpi_uninit_platform_driver(void) __exit; int dispc_init_platform_driver(void) __init; void dispc_uninit_platform_driver(void) __exit; void dispc_dump_clocks(struct seq_file *s); +u32 dispc_read_irqstatus(void); +void dispc_clear_irqstatus(u32 mask); +u32 dispc_read_irqenable(void); +void dispc_write_irqenable(u32 mask); int dispc_runtime_get(void); void dispc_runtime_put(void);