From patchwork Tue Oct 30 16:10:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1670971 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 77C8E3FD8C for ; Tue, 30 Oct 2012 16:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933960Ab2J3QKf (ORCPT ); Tue, 30 Oct 2012 12:10:35 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:56508 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933958Ab2J3QKd (ORCPT ); Tue, 30 Oct 2012 12:10:33 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9UGAX3B020101; Tue, 30 Oct 2012 11:10:33 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9UGAXwJ031823; Tue, 30 Oct 2012 11:10:33 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.1.323.3; Tue, 30 Oct 2012 11:10:32 -0500 Received: from deskari.tieu.ti.com (h68-16.vpn.ti.com [172.24.68.16]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9UGAHax009116; Tue, 30 Oct 2012 11:10:31 -0500 From: Tomi Valkeinen To: , , CC: , Tomi Valkeinen Subject: [PATCH 08/12] OMAPDSS: setup default dss fck Date: Tue, 30 Oct 2012 18:10:05 +0200 Message-ID: <1351613409-21186-9-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1351613409-21186-1-git-send-email-tomi.valkeinen@ti.com> References: <1351613409-21186-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org We don't currently set the dss fck when starting up. This is not a problem, as we setup the fck later when configuring the pixel clocks. Or this is how it was for omap2, for the rest of the omaps this may not be so. For DSI, HDMI and also for DPI when using DSI PLL, we don't need to change the dss fck, and thus it may be left unconfigured. Usually the dss fck is already setup fine by default, but we can't trust this. This patch sets the dss fck to maximum at probe time. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 5affa86..034cc1a 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -485,6 +485,36 @@ unsigned long dss_get_dpll4_rate(void) return 0; } +static int dss_setup_default_clock(void) +{ + unsigned long max_dss_fck, prate; + unsigned fck_div; + struct dss_clock_info dss_cinfo = { 0 }; + int r; + + if (dss.dpll4_m4_ck == NULL) + return 0; + + max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); + + prate = dss_get_dpll4_rate(); + + fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, + max_dss_fck); + + dss_cinfo.fck_div = fck_div; + + r = dss_calc_clock_rates(&dss_cinfo); + if (r) + return r; + + r = dss_set_clock_div(&dss_cinfo); + if (r) + return r; + + return 0; +} + int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo, struct dispc_clock_info *dispc_cinfo) { @@ -913,6 +943,10 @@ static int __init omap_dsshw_probe(struct platform_device *pdev) dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; + r = dss_setup_default_clock(); + if (r) + goto err_setup_clocks; + rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); @@ -923,6 +957,8 @@ static int __init omap_dsshw_probe(struct platform_device *pdev) return 0; +err_setup_clocks: + dss_runtime_put(); err_runtime_get: pm_runtime_disable(&pdev->dev); dss_put_clocks();