From patchwork Sat Nov 3 07:06:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar X-Patchwork-Id: 1691301 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id E94B1DFB7B for ; Sat, 3 Nov 2012 06:47:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751002Ab2KCGq7 (ORCPT ); Sat, 3 Nov 2012 02:46:59 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:25211 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751010Ab2KCGq7 (ORCPT ); Sat, 3 Nov 2012 02:46:59 -0400 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCW00H5SG5WIB60@mailout4.samsung.com> for linux-fbdev@vger.kernel.org; Sat, 03 Nov 2012 15:46:57 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.125]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 87.74.12699.1EDB4905; Sat, 03 Nov 2012 15:46:57 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-38-5094bde1dec4 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 47.74.12699.1EDB4905; Sat, 03 Nov 2012 15:46:57 +0900 (KST) Received: from localhost.localdomain ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCW00IESG60MA00@mmp2.samsung.com> for linux-fbdev@vger.kernel.org; Sat, 03 Nov 2012 15:46:57 +0900 (KST) From: Ajay Kumar To: linux-fbdev@vger.kernel.org, jg1.han@samsung.com Cc: FlorianSchandinat@gmx.de Subject: video: exynos_dp: Fix incorrect setting for INT_CTL Date: Sat, 03 Nov 2012 12:36:42 +0530 Message-id: <1351926402-25484-2-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1351926402-25484-1-git-send-email-ajaykumar.rs@samsung.com> References: <1351926402-25484-1-git-send-email-ajaykumar.rs@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDLMWRmVeSWpSXmKPExsWyRsSkVvfh3ikBBt3n1CxO9H1gdWD0+LxJ LoAxissmJTUnsyy1SN8ugStjyf8L7AWLuSuOfX7C1sC4n7OLkZNDQsBE4uu+o6wQtpjEhXvr 2boYuTiEBJYySkzd/pwNpujegY2MEInpjBIt63+zQjjLmSS+HL/PDFLFJqAtsW36TRYQWwSo Y+rf62DdzAIyEm/mL2ACsYUFbCSuTLoJFmcRUJXYsuU6WD2vgIfE7SUnoLYpSLQuO8QOYnMK eErs3dnKCGILAdU87fsG1Ssg8W3yIaBeDqB6WYlNB5hB7pEQuMwm8fZQCzvEHEmJgytusExg FF7AyLCKUTS1ILmgOCk910ivODG3uDQvXS85P3cTIzAIT/97Jr2DcVWDxSFGAQ5GJR5eA4kp AUKsiWXFlbmHGCU4mJVEeLvcgUK8KYmVValF+fFFpTmpxYcYfYAumcgsJZqcD4yQvJJ4Q2MT c1NjU0sjIzNTUxzCSuK8zR4pAUIC6YklqdmpqQWpRTDjmDg4pRoYmSeuS1jGe2z1g5eXUsIq Nl2tuuqvs+vBX6MIpzu9vPrt3V9+9Jyduz2hM/G9051df69VPg24urLwpnyHENNx1yMeQjzi 9pPvqe/ZdCdyi2Jy1OoJWcEPxZbOyT8Vx2AZ92LS3Wy/s/M/aCyo97+08PJthqM6EmLmfz0q fvt1Fj5/xz9Rb9WhuUosxRmJhlrMRcWJAIBU10pvAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e+xoO7DvVMCDI68lrI40feB1YHR4/Mm uQDGqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg qUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjCX/L7AXLOauOPb5CVsD 437OLkZODgkBE4l7BzYyQthiEhfurWfrYuTiEBKYzijRsv43K4SznEniy/H7zCBVbALaEtum 32QBsUWAuqf+vc4GYjMLyEi8mb+ACcQWFrCRuDLpJlicRUBVYsuW62D1vAIeEreXnGCD2KYg 0brsEDuIzSngKbF3ZyvYFUJANU/7vrFNYORdwMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93 EyM4xJ9J72Bc1WBxiFGAg1GJh9dAYkqAEGtiWXFl7iFGCQ5mJRHeLnegEG9KYmVValF+fFFp TmrxIUYfoKsmMkuJJucD4y+vJN7Q2MTc1NjU0sTCxMwSh7CSOG+zR0qAkEB6YklqdmpqQWoR zDgmDk6pBsaSjksTNvfsEmVQU/hWIn+NVTfcL3rFAfHG5x+3eTlFtu98oWUasfyFVkb6zacf 47kKudx1FwRtTpeXq17A9WXCzKBN+8JXLX/zTD1ozsTeapn+7RfztM+r5SX8C2P+e1TqZ8XG hf2plXM6/ibLKS0pUjMuss+wnu0lIOS0YmP9jwMbbmq1v1FiKc5INNRiLipOBADQ++SzngIA AA== X-CFilter-Loop: Reflected Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar --- drivers/video/exynos/exynos_dp_reg.c | 2 +- drivers/video/exynos/exynos_dp_reg.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 3f5ca8a..d67f49b 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c @@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp) void exynos_dp_init_interrupt(struct exynos_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); + writel(INT_POL0 | INT_POL1, dp->reg_base + EXYNOS_DP_INT_CTL); /* Clear pending regisers */ writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 1f2f014..fcf386e 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -242,7 +242,8 @@ /* EXYNOS_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) +#define INT_POL0 (0x1 << 0) +#define INT_POL1 (0x1 << 0) /* EXYNOS_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2)