From patchwork Mon Nov 5 07:42:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Kumar X-Patchwork-Id: 1695271 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id CD818DF2AB for ; Mon, 5 Nov 2012 07:23:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751560Ab2KEHX5 (ORCPT ); Mon, 5 Nov 2012 02:23:57 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:37006 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751107Ab2KEHX4 (ORCPT ); Mon, 5 Nov 2012 02:23:56 -0500 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD000GP275JWIT0@mailout1.samsung.com> for linux-fbdev@vger.kernel.org; Mon, 05 Nov 2012 16:23:55 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id F0.9C.12699.B8967905; Mon, 05 Nov 2012 16:23:55 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-53-5097698be0ee Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id B0.9C.12699.B8967905; Mon, 05 Nov 2012 16:23:55 +0900 (KST) Received: from localhost.localdomain ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD0001Q375OQO40@mmp1.samsung.com> for linux-fbdev@vger.kernel.org; Mon, 05 Nov 2012 16:23:55 +0900 (KST) From: Ajay Kumar To: linux-fbdev@vger.kernel.org, jg1.han@samsung.com Cc: FlorianSchandinat@gmx.de Subject: [PATCH V2] video: exynos_dp: Fix incorrect setting for INT_CTL Date: Mon, 05 Nov 2012 13:12:58 +0530 Message-id: <1352101378-11560-2-git-send-email-ajaykumar.rs@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1352101378-11560-1-git-send-email-ajaykumar.rs@samsung.com> References: <1352101378-11560-1-git-send-email-ajaykumar.rs@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkRrc7c3qAwe+ZEhYn+j6wOjB6fN4k F8AYxWWTkpqTWZZapG+XwJXR9ewCS8Fi7opfyx8xNTDu5+xi5OSQEDCR+N+2lR3CFpO4cG89 G4gtJLCUUaLxXG0XIwdYzdpmnS5GLqDwIkaJiy9XMEPULGeS6O/kAbHZBLQltk2/yQJiiwDV T/17HWwOs4CMxJv5C5hAbGEBd4n9Fy6A9bIIqEoc3LsJLM4r4CGxY/5DRogbFCRalx0Cu4dT wFNi57JbrBC7PCTaNt1ngugVkPg2+RALxG2yEpsOMIPcJiFwmU3i+/NPUHMkJQ6uuMEygVF4 ASPDKkbR1ILkguKk9FwjveLE3OLSvHS95PzcTYzA8Dv975n0DsZVDRaHGAU4GJV4eD9JTA8Q Yk0sK67MPcQowcGsJMLLwQAU4k1JrKxKLcqPLyrNSS0+xOgDdMlEZinR5HxgbOSVxBsam5ib GptaGhmZmZriEFYS5232SAkQEkhPLEnNTk0tSC2CGcfEwSnVwDjBJbZp2sTAZ1NuGf6cHWTG x39iz8wzVz8kNXQXhzu3Zl6zOjJ7U/qVLUJ+K4wnH1sskiivs/vN+VsX5lzboXnmd9K1l07f Y9uyxbhKM3tZ5/6dqnhBdYO1R/yUWMc/snVXdhmucNYvW+75+WD11s6rWku2WWsa/iy/KP7g 1R+GqkmCTWzsk3SVWIozEg21mIuKEwF0YJ6SbAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkkeLIzCtJLcpLzFFi42I5/e+xgG535vQAg4sfBSxO9H1gdWD0+LxJ LoAxqoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwdo qpJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsIYxo+vZBZaCxdwVv5Y/Ympg 3M/ZxcjBISFgIrG2WaeLkRPIFJO4cG89WxcjF4eQwCJGiYsvVzCDJIQEljNJ9HfygNhsAtoS 26bfZAGxRYB6p/69zgZiMwvISLyZv4AJxBYWcJfYf+ECWC+LgKrEwb2bwOK8Ah4SO+Y/ZIRY piDRuuwQO4jNKeApsXPZLVaIXR4SbZvuM01g5F3AyLCKUTS1ILmgOCk910ivODG3uDQvXS85 P3cTIzi8n0nvYFzVYHGIUYCDUYmH95PE9AAh1sSy4srcQ4wSHMxKIrwcDEAh3pTEyqrUovz4 otKc1OJDjD5AV01klhJNzgfGXl5JvKGxibmpsamliYWJmSUOYSVx3maPlAAhgfTEktTs1NSC 1CKYcUwcnFINjHF2eTK8K/7zVZiHhW59c26fUNv/8mtzxM/Jzxb8dtJDWW+ZkXGU72k283jW Z/N/B3Iv49ar+6O+btlyYQu/Zg35h7biCQdMp/wxrq+TeefV/98zJv65y0OTdP5kH3+xxZ+W z5h6SXipy4N9XWrxHhLvb1xP+Prqertzjbv1hWDF/3GXXyn2K7EUZyQaajEXFScCAPAASHuc AgAA X-CFilter-Loop: Reflected Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar --- drivers/video/exynos/exynos_dp_reg.c | 2 +- drivers/video/exynos/exynos_dp_reg.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 3f5ca8a..d67f49b 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c @@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp) void exynos_dp_init_interrupt(struct exynos_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); + writel(INT_POL0 | INT_POL1, dp->reg_base + EXYNOS_DP_INT_CTL); /* Clear pending regisers */ writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 1f2f014..8548b91 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -242,7 +242,8 @@ /* EXYNOS_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) +#define INT_POL0 (0x1 << 0) +#define INT_POL1 (0x1 << 1) /* EXYNOS_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2)