From patchwork Tue Jan 15 13:34:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 1978251 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id F1585DF2E5 for ; Tue, 15 Jan 2013 13:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757029Ab3AONeS (ORCPT ); Tue, 15 Jan 2013 08:34:18 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:46443 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756968Ab3AONeP (ORCPT ); Tue, 15 Jan 2013 08:34:15 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0FDY4Yn021545; Tue, 15 Jan 2013 07:34:05 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0FDY1GO005544; Tue, 15 Jan 2013 19:04:02 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Tue, 15 Jan 2013 19:04:01 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id r0FDXwVR003281; Tue, 15 Jan 2013 19:03:59 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id D7B1F158002; Tue, 15 Jan 2013 19:03:55 +0530 (IST) Received: from ubuntu-psp-linux.india.ext.ti.com (ubuntu-psp-linux [192.168.247.46]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r0FDXrR02787; Tue, 15 Jan 2013 19:03:54 +0530 (IST) From: Afzal Mohammed To: Paul Walmsley , Tony Lindgren , Russell King , Sekhar Nori , , , , Subject: [PATCH] ARM: AM33XX: clock: SET_RATE_PARENT in lcd path Date: Tue, 15 Jan 2013 19:04:57 +0530 Message-ID: <1358256897-26275-1-git-send-email-afzal@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org LCDC clock node is a one that does not have set rate capability. It just passes on the rate that is sent downstream by it's parent. While lcdc clock parent and it's grand parent - dpll_disp_m2_ck and dpll_disp_ck has the capability to configure rate. And the default rates provided by LCDC clock's ancestors are not sufficient to obtain pixel clock for current LCDC use cases, hence currently display would not work on AM335x SoC's (with driver modifications in platfrom independent way). Hence inform clock framework to propogate set rate for LCDC clock as well as it's parent - dpll_disp_m2_ck. With this change, set rate on LCDC clock would get propogated till dpll_disp_ck via dpll_disp_m2_ck, hence allowing the driver (same driver is used in DaVinci too) to set rates using LCDC clock without worrying about platform dependent clock details. Signed-off-by: Afzal Mohammed --- Based on v3.8-rc3 arch/arm/mach-omap2/cclock33xx_data.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index ea64ad6..b731216 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 * and ALT_CLK1/2) */ -DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0, - AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT, - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); +DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, + CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP, + AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); /* DPLL_PER */ static struct dpll_data dpll_per_dd = { @@ -932,6 +933,8 @@ int __init am33xx_clk_init(void) cpu_clkflg = CK_AM33XX; } + lcd_gclk.flags |= CLK_SET_RATE_PARENT; + for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk);