From patchwork Wed Jan 30 03:02:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 2065011 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 3C53B3FCD5 for ; Wed, 30 Jan 2013 03:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753225Ab3A3DCv (ORCPT ); Tue, 29 Jan 2013 22:02:51 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:13643 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752077Ab3A3DCo (ORCPT ); Tue, 29 Jan 2013 22:02:44 -0500 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 29 Jan 2013 19:02:31 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Tue, 29 Jan 2013 19:00:51 -0800 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Tue, 29 Jan 2013 19:00:51 -0800 Received: from percival.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.297.1; Tue, 29 Jan 2013 19:02:43 -0800 From: Alexandre Courbot To: Laurent Pinchart , Thierry Reding , Stephen Warren , Mark Zhang CC: , , , , Alexandre Courbot Subject: [RFC 2/4] tegra: ventana: add display and backlight DT nodes Date: Wed, 30 Jan 2013 12:02:17 +0900 Message-ID: <1359514939-15653-3-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1359514939-15653-1-git-send-email-acourbot@nvidia.com> References: <1359514939-15653-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Signed-off-by: Alexandre Courbot --- arch/arm/boot/dts/tegra20-ventana.dts | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index adc4754..48f4e6d 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -10,6 +10,16 @@ reg = <0x00000000 0x40000000>; }; + host1x { + dc@54200000 { + rgb { + status = "okay"; + nvidia,ddc-i2c-bus = <&lcd_ddc>; + nvidia,panel = <&panel>; + }; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -341,7 +351,7 @@ #size-cells = <0>; }; - i2c@1 { + lcd_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -516,6 +526,24 @@ bus-width = <8>; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <10>; + }; + + panel: panel { + compatible = "chunghwa,claa101wa01a"; + + pnl-supply = <&vdd_pnl_reg>; + pnl-enable-gpios = <&gpio 10 0>; + + bl-supply = <&vdd_bl_reg>; + bl-enable-gpios = <&gpio 28 0>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -549,7 +577,7 @@ enable-active-high; }; - regulator@3 { + vdd_pnl_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vdd_pnl"; @@ -559,7 +587,7 @@ enable-active-high; }; - regulator@4 { + vdd_bl_reg: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vdd_bl";