From patchwork Fri Sep 6 17:23:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawel Moll X-Patchwork-Id: 2854603 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A41689F494 for ; Fri, 6 Sep 2013 17:23:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF1C92038E for ; Fri, 6 Sep 2013 17:23:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A9DE020318 for ; Fri, 6 Sep 2013 17:23:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753696Ab3IFRX3 (ORCPT ); Fri, 6 Sep 2013 13:23:29 -0400 Received: from service87.mimecast.com ([91.220.42.44]:43227 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752412Ab3IFRX2 (ORCPT ); Fri, 6 Sep 2013 13:23:28 -0400 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Fri, 06 Sep 2013 18:23:27 +0100 Received: from hornet.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Sep 2013 18:23:24 +0100 From: Pawel Moll To: linux-fbdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Mark Rutland , Stephen Warren , Ian Campbell , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , Russell King , Arnd Bergmann , Pawel Moll Subject: [PATCH 2/2] ARM: vexpress: Add CLCD Device Tree properties Date: Fri, 6 Sep 2013 18:23:21 +0100 Message-Id: <1378488201-21146-2-git-send-email-pawel.moll@arm.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1378488201-21146-1-git-send-email-pawel.moll@arm.com> References: <1378488201-21146-1-git-send-email-pawel.moll@arm.com> X-OriginalArrivalTime: 06 Sep 2013 17:23:24.0999 (UTC) FILETIME=[CB1ABD70:01CEAB25] X-MC-Unique: 113090618232700201 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ... for V2M-P1 motherboard CLCD (limited to 640x480 16bpp and using dedicated video RAM bank) and for V2P-CA9 (up to 1024x768 16bpp). Signed-off-by: Pawel Moll --- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 25 +++++++++++++++++++++++-- arch/arm/boot/dts/vexpress-v2m.dtsi | 25 +++++++++++++++++++++++-- arch/arm/boot/dts/vexpress-v2p-ca9.dts | 20 ++++++++++++++++++++ 3 files changed, 66 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index ac870fb..91dff88 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -41,7 +41,7 @@ bank-width = <4>; }; - vram@2,00000000 { + v2m_vram: vram@2,00000000 { compatible = "arm,vexpress-vram"; reg = <2 0x00000000 0x00800000>; }; @@ -233,6 +233,27 @@ interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; + + video-ram = <&v2m_vram>; + max-framebuffer-size = <614400>; /* 640x480 16bpp */ + + /* This is the best the CLCD can do here */ + panel-type = "tft"; + panel-tft-interface = <8 8 8>; + display-timings { + native-mode = <&v2m_clcd_timing0>; + v2m_clcd_timing0: vga { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; @@ -282,7 +303,7 @@ /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; + freq-range = <23750000 65000000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index f142036..4bc348c 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -40,7 +40,7 @@ bank-width = <4>; }; - vram@3,00000000 { + v2m_vram: vram@3,00000000 { compatible = "arm,vexpress-vram"; reg = <3 0x00000000 0x00800000>; }; @@ -232,6 +232,27 @@ interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; + + video-ram = <&v2m_vram>; + max-framebuffer-size = <614400>; /* 640x480 16bpp */ + + /* This is the best the CLCD can do here */ + panel-type = "tft"; + panel-tft-interface = <8 8 8>; + display-timings { + native-mode = <&v2m_clcd_timing0>; + v2m_clcd_timing0: vga { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; @@ -281,7 +302,7 @@ /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; + freq-range = <23750000 65000000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 62d9b22..fbe1c998 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -73,6 +73,26 @@ interrupts = <0 44 4>; clocks = <&oscclk1>, <&oscclk2>; clock-names = "clcdclk", "apb_pclk"; + + max-framebuffer-size = <1572864>; /* 1024x768 16bpp */ + + /* This is the best the CLCD can do here */ + panel-type = "tft"; + panel-tft-interface = <8 8 8>; + display-timings { + native-mode = <&clcd_timing0>; + clcd_timing0: xga { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; }; memory-controller@100e0000 {