From patchwork Tue Sep 17 07:06:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 2901051 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6BC379F1C0 for ; Tue, 17 Sep 2013 07:07:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A495720347 for ; Tue, 17 Sep 2013 07:07:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A631A20336 for ; Tue, 17 Sep 2013 07:07:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752170Ab3IQHHi (ORCPT ); Tue, 17 Sep 2013 03:07:38 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:34365 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752129Ab3IQHHh (ORCPT ); Tue, 17 Sep 2013 03:07:37 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r8H77ac0018094; Tue, 17 Sep 2013 02:07:36 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8H77aVW024173; Tue, 17 Sep 2013 02:07:36 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.2.342.3; Tue, 17 Sep 2013 02:07:36 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id r8H77awF019818; Tue, 17 Sep 2013 02:07:36 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r8H77Yt25042; Tue, 17 Sep 2013 02:07:35 -0500 (CDT) From: Archit Taneja To: CC: , , Archit Taneja Subject: [PATCH 02/11] omapdss: HDMI: create a HDMI PLL library Date: Tue, 17 Sep 2013 12:36:28 +0530 Message-ID: <1379401597-27222-3-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1379401597-27222-1-git-send-email-archit@ti.com> References: <1379401597-27222-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP HDMI PLL is a block common to DSS in OMAP4, OMAP5 and DRA7x. Move the existing PLL functions from ti_hdmi_4xxx_ip.c and hdmi.c to a separate file. These funcs are called directly from the hdmi driver rather than hdmi_ip_ops function pointer calls. Add the PLL library function declarations to ti_hdmi.h. These will be shared amongst the omap4/5 hdmi platform drivers. Remove the PLL function pointer ops from the ti_hdmi_ip_ops struct. These will be shared amongst the omap4/5 hdmi platform drivers and other libraries. Signed-off-by: Archit Taneja --- drivers/video/omap2/dss/Makefile | 2 +- drivers/video/omap2/dss/dss_features.c | 3 - drivers/video/omap2/dss/hdmi.c | 65 ++------ drivers/video/omap2/dss/hdmi_pll.c | 243 ++++++++++++++++++++++++++++++ drivers/video/omap2/dss/ti_hdmi.h | 25 +-- drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 132 ---------------- 6 files changed, 267 insertions(+), 203 deletions(-) create mode 100644 drivers/video/omap2/dss/hdmi_pll.c diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile index 56ce6bd..5ea65d3 100644 --- a/drivers/video/omap2/dss/Makefile +++ b/drivers/video/omap2/dss/Makefile @@ -10,5 +10,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o -omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o hdmi_wp.o ti_hdmi_4xxx_ip.o +omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o hdmi_wp.o hdmi_pll.o ti_hdmi_4xxx_ip.o ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index db359e8..9ee92e9 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -797,10 +797,7 @@ static const struct ti_hdmi_ip_ops omap4_hdmi_functions = { .phy_enable = ti_hdmi_4xxx_phy_enable, .phy_disable = ti_hdmi_4xxx_phy_disable, .read_edid = ti_hdmi_4xxx_read_edid, - .pll_enable = ti_hdmi_4xxx_pll_enable, - .pll_disable = ti_hdmi_4xxx_pll_disable, .dump_core = ti_hdmi_4xxx_core_dump, - .dump_pll = ti_hdmi_4xxx_pll_dump, .dump_phy = ti_hdmi_4xxx_phy_dump, #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) .audio_start = ti_hdmi_4xxx_audio_start, diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index f2475fc..f6a2eba 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -42,7 +42,6 @@ #define HDMI_CORE_SYS 0x400 #define HDMI_CORE_AV 0x900 -#define HDMI_PLLCTRL 0x200 #define HDMI_PHY 0x300 /* HDMI EDID Length move this */ @@ -53,9 +52,6 @@ #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 -#define HDMI_DEFAULT_REGN 16 -#define HDMI_DEFAULT_REGM2 1 - static struct { struct mutex lock; struct platform_device *pdev; @@ -428,52 +424,6 @@ end: return cm; } -static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, - struct hdmi_pll_info *pi) -{ - unsigned long clkin, refclk; - u32 mf; - - clkin = clk_get_rate(hdmi.sys_clk) / 10000; - /* - * Input clock is predivided by N + 1 - * out put of which is reference clk - */ - - pi->regn = HDMI_DEFAULT_REGN; - - refclk = clkin / pi->regn; - - pi->regm2 = HDMI_DEFAULT_REGM2; - - /* - * multiplier is pixel_clk/ref_clk - * Multiplying by 100 to avoid fractional part removal - */ - pi->regm = phy * pi->regm2 / refclk; - - /* - * fractional multiplier is remainder of the difference between - * multiplier and actual phy(required pixel clock thus should be - * multiplied by 2^18(262144) divided by the reference clock - */ - mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; - pi->regmf = pi->regm2 * mf / refclk; - - /* - * Dcofreq should be set to 1 if required pixel clock - * is greater than 1000MHz - */ - pi->dcofreq = phy > 1000 * 100; - pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; - - /* Set the reference clock to sysclk reference */ - pi->refsel = HDMI_REFSEL_SYSCLK; - - DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); - DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); -} - static int hdmi_power_on_core(struct omap_dss_device *dssdev) { int r; @@ -526,12 +476,12 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) phy = p->pixel_clock; - hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); + hdmi_pll_compute(&hdmi.ip_data.pll, clk_get_rate(hdmi.sys_clk), phy); hdmi_wp_video_stop(&hdmi.ip_data.wp); /* config the PLL and PHY hdmi_set_pll_pwrfirst */ - r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); + r = hdmi_pll_enable(&hdmi.ip_data.pll, &hdmi.ip_data.wp); if (r) { DSSDBG("Failed to lock PLL\n"); goto err_pll_enable; @@ -566,7 +516,7 @@ err_mgr_enable: err_vid_enable: hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); err_phy_enable: - hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); + hdmi_pll_disable(&hdmi.ip_data.pll, &hdmi.ip_data.wp); err_pll_enable: hdmi_power_off_core(dssdev); return -EIO; @@ -580,7 +530,7 @@ static void hdmi_power_off_full(struct omap_dss_device *dssdev) hdmi_wp_video_stop(&hdmi.ip_data.wp); hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); - hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); + hdmi_pll_disable(&hdmi.ip_data.pll, &hdmi.ip_data.wp); hdmi_power_off_core(dssdev); } @@ -642,7 +592,7 @@ static void hdmi_dump_regs(struct seq_file *s) } hdmi_wp_dump(&hdmi.ip_data.wp, s); - hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); + hdmi_pll_dump(&hdmi.ip_data.pll, s); hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); @@ -1095,6 +1045,10 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) if (r) return r; + r = hdmi_pll_init(pdev, &hdmi.ip_data.pll); + if (r) + return r; + hdmi.ip_data.irq = platform_get_irq(pdev, 0); if (hdmi.ip_data.irq < 0) { DSSERR("platform_get_irq failed\n"); @@ -1111,7 +1065,6 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; hdmi.ip_data.core_av_offset = HDMI_CORE_AV; - hdmi.ip_data.pll_offset = HDMI_PLLCTRL; hdmi.ip_data.phy_offset = HDMI_PHY; hdmi_init_output(pdev); diff --git a/drivers/video/omap2/dss/hdmi_pll.c b/drivers/video/omap2/dss/hdmi_pll.c new file mode 100644 index 0000000..d53b8e2 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_pll.c @@ -0,0 +1,243 @@ +/* + * HDMI PLL + * + * Copyright (C) 2013 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include