From patchwork Thu Apr 24 10:17:17 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 4048001 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0AE7ABFF02 for ; Thu, 24 Apr 2014 10:19:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 20E472017D for ; Thu, 24 Apr 2014 10:19:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 37D372028D for ; Thu, 24 Apr 2014 10:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754261AbaDXKTt (ORCPT ); Thu, 24 Apr 2014 06:19:49 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:58154 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754598AbaDXKT3 (ORCPT ); Thu, 24 Apr 2014 06:19:29 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3OAJCil014445; Thu, 24 Apr 2014 05:19:12 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3OAJCTY021568; Thu, 24 Apr 2014 05:19:12 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Thu, 24 Apr 2014 05:19:11 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3OAISm9009835; Thu, 24 Apr 2014 05:19:09 -0500 From: Tomi Valkeinen To: Archit Taneja , , , CC: Tomi Valkeinen Subject: [PATCH 21/23] OMAPDSS: HDMI: PLL changes for OMAP5 Date: Thu, 24 Apr 2014 13:17:17 +0300 Message-ID: <1398334639-14172-22-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1398334639-14172-1-git-send-email-tomi.valkeinen@ti.com> References: <1398334639-14172-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Archit Taneja Add a features struct to differentiate between the HDMI PLLs on OMAP4 and OMAP5. The OMAP5 PLL is more sensitive when it comes to locking. We need to ensure that the DCO freq isn't too low for lower pixel clocks. Modify the PLL computation slightly to ensure the HDMI PLL locks for lower frequencies. This will be later replaced by a more complex computation which makes sure all the PLL constraints are met. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi_pll.c | 81 +++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/hdmi_pll.c b/drivers/video/fbdev/omap2/dss/hdmi_pll.c index 5fc71215c303..2b910cb9eee4 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_pll.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_pll.c @@ -23,6 +23,18 @@ #define HDMI_DEFAULT_REGN 16 #define HDMI_DEFAULT_REGM2 1 +struct hdmi_pll_features { + bool sys_reset; + /* this is a hack, need to replace it with a better computation of M2 */ + bool bound_dcofreq; + unsigned long fint_min, fint_max; + u16 regm_max; + unsigned long dcofreq_low_min, dcofreq_low_max; + unsigned long dcofreq_high_min, dcofreq_high_max; +}; + +static const struct hdmi_pll_features *pll_feat; + void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) { #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\ @@ -57,7 +69,11 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy) refclk = clkin / pi->regn; - pi->regm2 = HDMI_DEFAULT_REGM2; + /* temorary hack to make sure DCO freq isn't calculated too low */ + if (pll_feat->bound_dcofreq && phy <= 65000) + pi->regm2 = 3; + else + pi->regm2 = HDMI_DEFAULT_REGM2; /* * multiplier is pixel_clk/ref_clk @@ -154,7 +170,7 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll) static int hdmi_pll_reset(struct hdmi_pll_data *pll) { /* SYSRESET controlled by power FSM */ - REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 3, 3); + REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, pll_feat->sys_reset, 3, 3); /* READ 0x0 reset is in progress */ if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1) @@ -197,11 +213,72 @@ void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) #define PLL_OFFSET 0x200 #define PLL_SIZE 0x100 +static const struct hdmi_pll_features omap44xx_pll_feats = { + .sys_reset = false, + .bound_dcofreq = false, + .fint_min = 500000, + .fint_max = 2500000, + .regm_max = 4095, + .dcofreq_low_min = 500000000, + .dcofreq_low_max = 1000000000, + .dcofreq_high_min = 1000000000, + .dcofreq_high_max = 2000000000, +}; + +static const struct hdmi_pll_features omap54xx_pll_feats = { + .sys_reset = true, + .bound_dcofreq = true, + .fint_min = 620000, + .fint_max = 2500000, + .regm_max = 2046, + .dcofreq_low_min = 750000000, + .dcofreq_low_max = 1500000000, + .dcofreq_high_min = 1250000000, + .dcofreq_high_max = 2500000000UL, +}; + +static int hdmi_pll_init_features(struct platform_device *pdev) +{ + struct hdmi_pll_features *dst; + const struct hdmi_pll_features *src; + + dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); + if (!dst) { + dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n"); + return -ENOMEM; + } + + switch (omapdss_get_version()) { + case OMAPDSS_VER_OMAP4430_ES1: + case OMAPDSS_VER_OMAP4430_ES2: + case OMAPDSS_VER_OMAP4: + src = &omap44xx_pll_feats; + break; + + case OMAPDSS_VER_OMAP5: + src = &omap54xx_pll_feats; + break; + + default: + return -ENODEV; + } + + memcpy(dst, src, sizeof(*dst)); + pll_feat = dst; + + return 0; +} + int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll) { + int r; struct resource *res; struct resource temp_res; + r = hdmi_pll_init_features(pdev); + if (r) + return r; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); if (!res) { DSSDBG("can't get PLL mem resource by name\n");