From patchwork Fri Oct 24 10:37:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 5145531 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8839C9F349 for ; Fri, 24 Oct 2014 10:38:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9DC7F200D9 for ; Fri, 24 Oct 2014 10:38:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B77A920279 for ; Fri, 24 Oct 2014 10:38:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755855AbaJXKiG (ORCPT ); Fri, 24 Oct 2014 06:38:06 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:59923 "EHLO mail-pd0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756225AbaJXKiF (ORCPT ); Fri, 24 Oct 2014 06:38:05 -0400 Received: by mail-pd0-f182.google.com with SMTP id y10so1218521pdj.41 for ; Fri, 24 Oct 2014 03:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0oT5yqa/rXhySmtUmXodsjU3qSFrOiXewvmw/U3VjPA=; b=OPZ1550rAHdC79Rec4LUoF67vRfLZsYlvdJ8zfl75Zu0sA8WQrvyg8K5meDSxBexoB J055m3JUHv+d4AzyZlpjjYeD4B5x49AlHEY52RHCfmmwd5D5rD5CC7NhMUo0/c9VkAHm VT5QHRDwbDuy4zm6P7/0f0F7UlrlF0rj0w1fwHDGwqU1uRR9WsR/BXmw3il2Xy7qITjF MQYbwnGX5F8Zz4m0BKh8FoZ83ZON0ZI2/owQ9vgQBlt9e7TLkQhiC0lc8TEXtFTX2roK 3hwq7TXjuYr68jMuzkulJ5CYej6brej12XwymkxLlJ9ySDhQWLAD0w5KNomV9d8lV/Ft kGWA== X-Received: by 10.70.61.68 with SMTP id n4mr3799015pdr.60.1414147084688; Fri, 24 Oct 2014 03:38:04 -0700 (PDT) Received: from fangorn.rup.mentorg.com (nat-min.mentorg.com. [139.181.32.34]) by mx.google.com with ESMTPSA id jc3sm3590019pbb.49.2014.10.24.03.38.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Oct 2014 03:38:04 -0700 (PDT) From: Dmitry Eremin-Solenikov To: linux-arm-kernel@lists.infradead.org, linux-pcmcia@lists.infradead.org, linux-fbdev@vger.kernel.org Cc: Russell King , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , Linus Walleij , Andrea Adami Subject: [PATCH 1/5] arm: sa1100: add cpu clock Date: Fri, 24 Oct 2014 14:37:23 +0400 Message-Id: <1414147047-12892-2-git-send-email-dbaryshkov@gmail.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1414147047-12892-1-git-send-email-dbaryshkov@gmail.com> References: <1414147047-12892-1-git-send-email-dbaryshkov@gmail.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Both SA1100 framebuffer and PCMCIA drivers require knowledge of cpu frequency to correctly program timings. Currently they receive timing information by calling cpufreq_get(0). However if cpu frequency driver is not enabled (e.g. due to unsupported DRAM chip/board on sa1110) cpufreq_get(0) returns 0, causing incorrect timings to be programmed. Add cpu clock returning cpu frequency, to be used by sa11x0 fb and pcmcia drivers. Signed-off-by: Dmitry Eremin-Solenikov --- arch/arm/mach-sa1100/clock.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index 9fa6a99..53f750d 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -15,10 +15,12 @@ #include #include +#include struct clkops { void (*enable)(struct clk *); void (*disable)(struct clk *); + unsigned long (*get_rate)(struct clk *); }; struct clk { @@ -33,13 +35,6 @@ struct clk clk_##_name = { \ static DEFINE_SPINLOCK(clocks_lock); -/* Dummy clk routine to build generic kernel parts that may be using them */ -unsigned long clk_get_rate(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - static void clk_gpio27_enable(struct clk *clk) { /* @@ -58,6 +53,19 @@ static void clk_gpio27_disable(struct clk *clk) GAFR &= ~GPIO_32_768kHz; } +static void clk_cpu_enable(struct clk *clk) +{ +} + +static void clk_cpu_disable(struct clk *clk) +{ +} + +static unsigned long clk_cpu_get_rate(struct clk *clk) +{ + return sa11x0_getspeed(0) * 1000; +} + int clk_enable(struct clk *clk) { unsigned long flags; @@ -87,16 +95,35 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk && clk->ops && clk->ops->get_rate) + return clk->ops->get_rate(clk); + + return 0; +} +EXPORT_SYMBOL(clk_get_rate); + const struct clkops clk_gpio27_ops = { .enable = clk_gpio27_enable, .disable = clk_gpio27_disable, }; +const struct clkops clk_cpu_ops = { + .enable = clk_cpu_enable, + .disable = clk_cpu_disable, + .get_rate = clk_cpu_get_rate, +}; + static DEFINE_CLK(gpio27, &clk_gpio27_ops); +static DEFINE_CLK(cpu, &clk_cpu_ops); + static struct clk_lookup sa11xx_clkregs[] = { CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), CLKDEV_INIT("sa1100-rtc", NULL, NULL), + CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), + CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), }; static int __init sa11xx_clk_init(void)