From patchwork Thu Nov 6 07:41:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 5239531 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 657D69FD45 for ; Thu, 6 Nov 2014 07:41:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89AD92010C for ; Thu, 6 Nov 2014 07:41:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A5604200D6 for ; Thu, 6 Nov 2014 07:41:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751234AbaKFHlo (ORCPT ); Thu, 6 Nov 2014 02:41:44 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:48960 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751141AbaKFHln (ORCPT ); Thu, 6 Nov 2014 02:41:43 -0500 Received: by mail-wi0-f178.google.com with SMTP id bs8so597858wib.17 for ; Wed, 05 Nov 2014 23:41:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0oT5yqa/rXhySmtUmXodsjU3qSFrOiXewvmw/U3VjPA=; b=bhQM+979KtYci4JDs3qTkh33horYU5mK15u5MT/ZtMov8XACQS/UIfd28TVkouEVQS vl4JpcIKvugqJetintEw3ex1+qbrK9uWFIJ0mrVYr5XguV6Vclnrm6rv8c7W8Vu47hmy yjIGZUG8opPlIdj+8vRIEEPGmBynf88Wk8fXH1WJozo3KUqyrYwXxRXhj31x9FR5KyZT xjkpJEQ33pIp4swXLyhyZLWRW54Z7W7UcpEvPVa7gb3Z59KJmFm0CBI5LeeqZ4fj7nMf UElI6t0lAP0hGtBcBuOPJMFA0OLLXLB4PYIVFpELeIaAx+sFeZI9ZZBOacHZH/r1fH/C sWgA== X-Received: by 10.180.11.168 with SMTP id r8mr11903195wib.74.1415259702490; Wed, 05 Nov 2014 23:41:42 -0800 (PST) Received: from fangorn.rup.mentorg.com (nat-min.mentorg.com. [139.181.32.34]) by mx.google.com with ESMTPSA id gy4sm7236302wib.11.2014.11.05.23.41.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Nov 2014 23:41:41 -0800 (PST) From: Dmitry Eremin-Solenikov To: Russell King Cc: linux-pcmcia@lists.infradead.org, linux-fbdev@vger.kernel.org, Andrea Adami , Linus Walleij Subject: [PATCH RESEND 1/5] arm: sa1100: add cpu clock Date: Thu, 6 Nov 2014 10:41:13 +0300 Message-Id: <1415259677-18770-2-git-send-email-dbaryshkov@gmail.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1415259677-18770-1-git-send-email-dbaryshkov@gmail.com> References: <1415259677-18770-1-git-send-email-dbaryshkov@gmail.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, SUSPICIOUS_RECIPS, T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Both SA1100 framebuffer and PCMCIA drivers require knowledge of cpu frequency to correctly program timings. Currently they receive timing information by calling cpufreq_get(0). However if cpu frequency driver is not enabled (e.g. due to unsupported DRAM chip/board on sa1110) cpufreq_get(0) returns 0, causing incorrect timings to be programmed. Add cpu clock returning cpu frequency, to be used by sa11x0 fb and pcmcia drivers. Signed-off-by: Dmitry Eremin-Solenikov --- arch/arm/mach-sa1100/clock.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index 9fa6a99..53f750d 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -15,10 +15,12 @@ #include #include +#include struct clkops { void (*enable)(struct clk *); void (*disable)(struct clk *); + unsigned long (*get_rate)(struct clk *); }; struct clk { @@ -33,13 +35,6 @@ struct clk clk_##_name = { \ static DEFINE_SPINLOCK(clocks_lock); -/* Dummy clk routine to build generic kernel parts that may be using them */ -unsigned long clk_get_rate(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - static void clk_gpio27_enable(struct clk *clk) { /* @@ -58,6 +53,19 @@ static void clk_gpio27_disable(struct clk *clk) GAFR &= ~GPIO_32_768kHz; } +static void clk_cpu_enable(struct clk *clk) +{ +} + +static void clk_cpu_disable(struct clk *clk) +{ +} + +static unsigned long clk_cpu_get_rate(struct clk *clk) +{ + return sa11x0_getspeed(0) * 1000; +} + int clk_enable(struct clk *clk) { unsigned long flags; @@ -87,16 +95,35 @@ void clk_disable(struct clk *clk) } EXPORT_SYMBOL(clk_disable); +unsigned long clk_get_rate(struct clk *clk) +{ + if (clk && clk->ops && clk->ops->get_rate) + return clk->ops->get_rate(clk); + + return 0; +} +EXPORT_SYMBOL(clk_get_rate); + const struct clkops clk_gpio27_ops = { .enable = clk_gpio27_enable, .disable = clk_gpio27_disable, }; +const struct clkops clk_cpu_ops = { + .enable = clk_cpu_enable, + .disable = clk_cpu_disable, + .get_rate = clk_cpu_get_rate, +}; + static DEFINE_CLK(gpio27, &clk_gpio27_ops); +static DEFINE_CLK(cpu, &clk_cpu_ops); + static struct clk_lookup sa11xx_clkregs[] = { CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), CLKDEV_INIT("sa1100-rtc", NULL, NULL), + CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), + CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), }; static int __init sa11xx_clk_init(void)