From patchwork Wed Nov 12 11:52:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5288461 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7A051C11AD for ; Wed, 12 Nov 2014 11:53:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A0C1720166 for ; Wed, 12 Nov 2014 11:53:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA38020172 for ; Wed, 12 Nov 2014 11:53:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752626AbaKLLxP (ORCPT ); Wed, 12 Nov 2014 06:53:15 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:36458 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752611AbaKLLxN (ORCPT ); Wed, 12 Nov 2014 06:53:13 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id sACBrCAO023477; Wed, 12 Nov 2014 05:53:12 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id sACBrCsB026783; Wed, 12 Nov 2014 05:53:12 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 12 Nov 2014 05:53:13 -0600 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id sACBqgIG031206; Wed, 12 Nov 2014 05:53:11 -0600 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 19/22] OMAPDSS: HDMI: split PLL enable & config Date: Wed, 12 Nov 2014 13:52:21 +0200 Message-ID: <1415793144-11723-20-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1415793144-11723-1-git-send-email-tomi.valkeinen@ti.com> References: <1415793144-11723-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At the moment we have one function, hdmi_pll_enable, which enables the PLL and writes the PLL configuration to registers. To make the HDMI PLL ahere to the DSS PLL API, split the hdmi_pll_enable into two parts: hdmi_pll_enable which enables the PLL HW, and hdmi_pll_set_config which writes the config. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi.h | 1 + drivers/video/fbdev/omap2/dss/hdmi4.c | 10 ++++++++-- drivers/video/fbdev/omap2/dss/hdmi5.c | 10 ++++++++-- drivers/video/fbdev/omap2/dss/hdmi_pll.c | 6 +----- 4 files changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index 03761ecb81a6..7595274a9bcf 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h @@ -316,6 +316,7 @@ int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); /* HDMI PLL funcs */ int hdmi_pll_enable(struct hdmi_pll_data *pll); void hdmi_pll_disable(struct hdmi_pll_data *pll); +int hdmi_pll_set_config(struct hdmi_pll_data *pll); void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, unsigned long target_tmds); diff --git a/drivers/video/fbdev/omap2/dss/hdmi4.c b/drivers/video/fbdev/omap2/dss/hdmi4.c index 2094b6eae99e..98aa910241b8 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4.c @@ -196,13 +196,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock); - /* config the PLL and PHY hdmi_set_pll_pwrfirst */ r = hdmi_pll_enable(&hdmi.pll); if (r) { - DSSDBG("Failed to lock PLL\n"); + DSSERR("Failed to enable PLL\n"); goto err_pll_enable; } + r = hdmi_pll_set_config(&hdmi.pll); + if (r) { + DSSERR("Failed to configure PLL\n"); + goto err_pll_cfg; + } + r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco, hdmi.pll.info.clkout); if (r) { @@ -241,6 +246,7 @@ err_vid_enable: err_phy_cfg: hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); err_phy_pwr: +err_pll_cfg: hdmi_pll_disable(&hdmi.pll); err_pll_enable: hdmi_power_off_core(dssdev); diff --git a/drivers/video/fbdev/omap2/dss/hdmi5.c b/drivers/video/fbdev/omap2/dss/hdmi5.c index fb8c14507a4d..facc4e070520 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi5.c +++ b/drivers/video/fbdev/omap2/dss/hdmi5.c @@ -214,13 +214,18 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) hdmi_wp_set_irqstatus(&hdmi.wp, hdmi_wp_get_irqstatus(&hdmi.wp)); - /* config the PLL and PHY hdmi_set_pll_pwrfirst */ r = hdmi_pll_enable(&hdmi.pll); if (r) { - DSSDBG("Failed to lock PLL\n"); + DSSERR("Failed to enable PLL\n"); goto err_pll_enable; } + r = hdmi_pll_set_config(&hdmi.pll); + if (r) { + DSSERR("Failed to configure PLL\n"); + goto err_pll_cfg; + } + r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco, hdmi.pll.info.clkout); if (r) { @@ -259,6 +264,7 @@ err_vid_enable: hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); err_phy_pwr: err_phy_cfg: +err_pll_cfg: hdmi_pll_disable(&hdmi.pll); err_pll_enable: hdmi_power_off_core(dssdev); diff --git a/drivers/video/fbdev/omap2/dss/hdmi_pll.c b/drivers/video/fbdev/omap2/dss/hdmi_pll.c index 190bede1dcb9..c14c3d132513 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_pll.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_pll.c @@ -103,7 +103,7 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, pi->clkout = clkout; } -static int hdmi_pll_config(struct hdmi_pll_data *pll) +int hdmi_pll_set_config(struct hdmi_pll_data *pll) { u32 r; struct hdmi_pll_info *fmt = &pll->info; @@ -179,10 +179,6 @@ int hdmi_pll_enable(struct hdmi_pll_data *pll) if (r) return r; - r = hdmi_pll_config(pll); - if (r) - return r; - return 0; }