From patchwork Tue Jan 27 10:50:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5715991 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 256DDC058D for ; Tue, 27 Jan 2015 10:51:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4EB1120211 for ; Tue, 27 Jan 2015 10:51:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4416220225 for ; Tue, 27 Jan 2015 10:51:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757966AbbA0KvQ (ORCPT ); Tue, 27 Jan 2015 05:51:16 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:60770 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757812AbbA0KvN (ORCPT ); Tue, 27 Jan 2015 05:51:13 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t0RApCfr028948; Tue, 27 Jan 2015 04:51:12 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t0RApBuB016196; Tue, 27 Jan 2015 04:51:11 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Tue, 27 Jan 2015 04:51:10 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t0RAoqLg013652; Tue, 27 Jan 2015 04:51:10 -0600 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 13/14] OMAPDSS: HDMI: Add DRA7xx support Date: Tue, 27 Jan 2015 12:50:41 +0200 Message-ID: <1422355842-11234-14-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1422355842-11234-1-git-send-email-tomi.valkeinen@ti.com> References: <1422355842-11234-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for DRA7xx to the HDMI driver. The HDMI block on DRA7xx is the same as on OMAP5, except we need to enable and disable the HDMI PLL via the CONTROL module. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi5.c | 1 + drivers/video/fbdev/omap2/dss/hdmi_phy.c | 1 + drivers/video/fbdev/omap2/dss/hdmi_pll.c | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/drivers/video/fbdev/omap2/dss/hdmi5.c b/drivers/video/fbdev/omap2/dss/hdmi5.c index 39aae3aa7136..3f0b34a7031a 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi5.c +++ b/drivers/video/fbdev/omap2/dss/hdmi5.c @@ -787,6 +787,7 @@ static const struct dev_pm_ops hdmi_pm_ops = { static const struct of_device_id hdmi_of_match[] = { { .compatible = "ti,omap5-hdmi", }, + { .compatible = "ti,dra7-hdmi", }, {}, }; diff --git a/drivers/video/fbdev/omap2/dss/hdmi_phy.c b/drivers/video/fbdev/omap2/dss/hdmi_phy.c index bc9e07d2afbe..1f5d19c119ce 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_phy.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_phy.c @@ -208,6 +208,7 @@ static int hdmi_phy_init_features(struct platform_device *pdev) break; case OMAPDSS_VER_OMAP5: + case OMAPDSS_VER_DRA7xx: src = &omap54xx_phy_feats; break; diff --git a/drivers/video/fbdev/omap2/dss/hdmi_pll.c b/drivers/video/fbdev/omap2/dss/hdmi_pll.c index b808f7c72d83..06e23a7c432c 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_pll.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_pll.c @@ -104,6 +104,8 @@ static int hdmi_pll_enable(struct dss_pll *dsspll) struct hdmi_wp_data *wp = pll->wp; u16 r = 0; + dss_ctrl_pll_enable(DSS_PLL_HDMI, true); + r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); if (r) return r; @@ -117,6 +119,8 @@ static void hdmi_pll_disable(struct dss_pll *dsspll) struct hdmi_wp_data *wp = pll->wp; hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); + + dss_ctrl_pll_enable(DSS_PLL_HDMI, false); } static const struct dss_pll_ops dsi_pll_ops = { @@ -197,6 +201,7 @@ static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data break; case OMAPDSS_VER_OMAP5: + case OMAPDSS_VER_DRA7xx: pll->hw = &dss_omap5_hdmi_pll_hw; break;