From patchwork Thu Feb 26 12:49:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5891871 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 302929F399 for ; Thu, 26 Feb 2015 12:49:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5DCAF20390 for ; Thu, 26 Feb 2015 12:49:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1847E203A5 for ; Thu, 26 Feb 2015 12:49:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932234AbbBZMts (ORCPT ); Thu, 26 Feb 2015 07:49:48 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:37398 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932213AbbBZMtr (ORCPT ); Thu, 26 Feb 2015 07:49:47 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1QCnkgi026071; Thu, 26 Feb 2015 06:49:46 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1QCnjOG030441; Thu, 26 Feb 2015 06:49:45 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Thu, 26 Feb 2015 06:49:45 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1QCnUhS030427; Thu, 26 Feb 2015 06:49:44 -0600 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 11/15] OMAPDSS: setup default fifo thresholds Date: Thu, 26 Feb 2015 14:49:05 +0200 Message-ID: <1424954949-12801-11-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1424954949-12801-1-git-send-email-tomi.valkeinen@ti.com> References: <1424954949-12801-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At the moment we don't setup FIFO thresholds by default in omapdss. It's supposed to be done by the user of omapdss. And that is missing from omapdrm, causing unoptimal thresholds to be used when using omapdrm. While I believe it's in theory better to allow the user of omapdss to setup the fifo thresholds, in practice we always use the same values, and we could as well setup the thresholds in omapdss. Furthermore, in omapdss init we always swap the FIFO used for GFX and WB overlays, but we don't swap the FIFO thresholds for those overlays (which is the reason for omapdrm using unoptimal HW reset values). So it would make sense to setup the thresholds to account for the swapping of the FIFOs. So, this patch adds code to setup default FIFO tresholds at omapdss init. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/dispc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index 766c985cbfa7..6296a3e5124f 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -1138,6 +1138,7 @@ static void dispc_init_fifos(void) int fifo; u8 start, end; u32 unit; + int i; unit = dss_feat_get_buffer_size_unit(); @@ -1177,6 +1178,20 @@ static void dispc_init_fifos(void) dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; } + + /* + * Setup default fifo thresholds. + */ + for (i = 0; i < dss_feat_get_num_ovls(); ++i) { + u32 low, high; + const bool use_fifomerge = false; + const bool manual_update = false; + + dispc_ovl_compute_fifo_thresholds(i, &low, &high, + use_fifomerge, manual_update); + + dispc_ovl_set_fifo_threshold(i, low, high); + } } static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)