From patchwork Thu Feb 26 12:49:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5891891 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1BE0DBF6C3 for ; Thu, 26 Feb 2015 12:49:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3A9FB20390 for ; Thu, 26 Feb 2015 12:49:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A8DC203A1 for ; Thu, 26 Feb 2015 12:49:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932213AbbBZMtt (ORCPT ); Thu, 26 Feb 2015 07:49:49 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:33810 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932194AbbBZMtk (ORCPT ); Thu, 26 Feb 2015 07:49:40 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1QCne63029796; Thu, 26 Feb 2015 06:49:40 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1QCndWa016676; Thu, 26 Feb 2015 06:49:39 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Thu, 26 Feb 2015 06:49:38 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1QCnUhN030427; Thu, 26 Feb 2015 06:49:37 -0600 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 06/15] OMAPDSS: DISPC: explicit handling for sync and de levels Date: Thu, 26 Feb 2015 14:49:00 +0200 Message-ID: <1424954949-12801-6-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1424954949-12801-1-git-send-email-tomi.valkeinen@ti.com> References: <1424954949-12801-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When configuring the lcd timings, instead of writing enum values directly to the HW, use switch-case to get the value to be programmed. This is safer and also allows us to change the enum values. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/dispc.c | 41 +++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index 11bd780fcdfa..8805266a52f4 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -2915,7 +2915,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, { u32 timing_h, timing_v, l; - bool onoff, rf, ipc; + bool onoff, rf, ipc, vs, hs, de; timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | @@ -2927,6 +2927,39 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, dispc_write_reg(DISPC_TIMING_H(channel), timing_h); dispc_write_reg(DISPC_TIMING_V(channel), timing_v); + switch (vsync_level) { + case OMAPDSS_SIG_ACTIVE_LOW: + vs = true; + break; + case OMAPDSS_SIG_ACTIVE_HIGH: + vs = false; + break; + default: + BUG(); + } + + switch (hsync_level) { + case OMAPDSS_SIG_ACTIVE_LOW: + hs = true; + break; + case OMAPDSS_SIG_ACTIVE_HIGH: + hs = false; + break; + default: + BUG(); + } + + switch (de_level) { + case OMAPDSS_SIG_ACTIVE_LOW: + de = true; + break; + case OMAPDSS_SIG_ACTIVE_HIGH: + de = false; + break; + default: + BUG(); + } + switch (data_pclk_edge) { case OMAPDSS_DRIVE_SIG_RISING_EDGE: ipc = false; @@ -2954,10 +2987,10 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, l = FLD_VAL(onoff, 17, 17) | FLD_VAL(rf, 16, 16) | - FLD_VAL(de_level, 15, 15) | + FLD_VAL(de, 15, 15) | FLD_VAL(ipc, 14, 14) | - FLD_VAL(hsync_level, 13, 13) | - FLD_VAL(vsync_level, 12, 12); + FLD_VAL(hs, 13, 13) | + FLD_VAL(vs, 12, 12); dispc_write_reg(DISPC_POL_FREQ(channel), l);