From patchwork Wed Dec 9 15:59:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 7809711 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 85F36BEEE5 for ; Wed, 9 Dec 2015 16:00:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B0D72203C1 for ; Wed, 9 Dec 2015 16:00:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CD639204B0 for ; Wed, 9 Dec 2015 16:00:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750945AbbLIQAT (ORCPT ); Wed, 9 Dec 2015 11:00:19 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:53942 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751796AbbLIQAL (ORCPT ); Wed, 9 Dec 2015 11:00:11 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id tB9G09PG022800; Wed, 9 Dec 2015 10:00:09 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id tB9G07Kk029130; Wed, 9 Dec 2015 10:00:09 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Wed, 9 Dec 2015 10:00:06 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id tB9G02K5028647; Wed, 9 Dec 2015 10:00:06 -0600 From: Tomi Valkeinen To: , Laurent Pinchart CC: Tomi Valkeinen Subject: [PATCH 02/23] OMAPDSS: DISPC: always set ALIGN when available Date: Wed, 9 Dec 2015 17:59:30 +0200 Message-ID: <1449676791-26304-3-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1449676791-26304-1-git-send-email-tomi.valkeinen@ti.com> References: <1449676791-26304-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP By default DISPC asserts hsync and vsync sequentially, i.e. there's first hsync and that is immediately followed by vsync. This is the only available behaviour on OMAP2/3, and default behaviour on OMAP4+. OMAP4+ has ALIGN bit in POL_FREQ register, which makes DISPC assert both syncs at the same time. It has been observed that some panels don't like sequential syncs (AM5 EVM's panel). After studying the datasheets for multiple panels and encoders, and MIPI DPI spec, it looks like there is no standard way to handle this. Sometimes the datasheets don't mention the required syncs behaviour at all, sometimes the datasheets have images that hint towards simultaneous syncs, and sometimes it is explicitly mentioned that simultaneous syncs are needed. No panels or encoders requiring sequential sync was found. It thus seems to be safe to default to simultaneous syncs when the ALIGN bit is available. This fixed AM5 EVM's panel, and no side effects have been observed on other panels or encoders. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/dispc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index be716c9ffb88..ced6050666cc 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c @@ -99,6 +99,9 @@ struct dispc_features { /* PIXEL_INC is not added to the last pixel of a line */ bool last_pixel_inc_missing:1; + + /* POL_FREQ has ALIGN bit */ + bool supports_sync_align:1; }; #define DISPC_MAX_NR_FIFOS 5 @@ -3163,6 +3166,10 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, FLD_VAL(hs, 13, 13) | FLD_VAL(vs, 12, 12); + /* always set ALIGN bit when available */ + if (dispc.feat->supports_sync_align) + l |= (1 << 18); + dispc_write_reg(DISPC_POL_FREQ(channel), l); if (dispc.syscon_pol) { @@ -3854,6 +3861,7 @@ static const struct dispc_features omap44xx_dispc_feats = { .num_fifos = 5, .gfx_fifo_workaround = true, .set_max_preload = true, + .supports_sync_align = true, }; static const struct dispc_features omap54xx_dispc_feats = { @@ -3875,6 +3883,7 @@ static const struct dispc_features omap54xx_dispc_feats = { .gfx_fifo_workaround = true, .mstandby_workaround = true, .set_max_preload = true, + .supports_sync_align = true, }; static int dispc_init_features(struct platform_device *pdev)