From patchwork Tue Mar 1 19:18:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ondrej Zary X-Patchwork-Id: 600481 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p21JJGIJ026785 for ; Tue, 1 Mar 2011 19:19:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757118Ab1CATSh (ORCPT ); Tue, 1 Mar 2011 14:18:37 -0500 Received: from mail1-out1.atlantis.sk ([80.94.52.55]:33641 "EHLO mail.atlantis.sk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1757115Ab1CATSf (ORCPT ); Tue, 1 Mar 2011 14:18:35 -0500 Received: (qmail 17389 invoked from network); 1 Mar 2011 19:18:37 -0000 Received: from unknown (HELO pentium) (rainbow@rainbow-software.org@85.216.180.141) by mail.atlantis.sk with AES256-SHA encrypted SMTP; 1 Mar 2011 19:18:37 -0000 From: Ondrej Zary To: Ondrej Zajicek Subject: [PATCH 3/5] s3fb: fix 15/16bpp modes with over 115MHz pixclocks on 86C365 Trio3D Date: Tue, 1 Mar 2011 20:18:27 +0100 User-Agent: KMail/1.9.10 Cc: linux-fbdev@vger.kernel.org, Kernel development list MIME-Version: 1.0 Content-Disposition: inline Message-Id: <201103012018.30651.linux@rainbow-software.org> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Tue, 01 Mar 2011 19:19:16 +0000 (UTC) --- linux-2.6.38-rc4-/drivers/video/s3fb.c 2011-02-20 20:48:41.000000000 +0100 +++ linux-2.6.38-rc4/drivers/video/s3fb.c 2011-02-22 23:31:16.000000000 +0100 @@ -675,6 +675,15 @@ svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); @@ -691,6 +700,15 @@ svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); else svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + } else if (par->chip == CHIP_365_TRIO3D) { + svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); + if (info->var.pixclock > 8695) { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); + hmul = 2; + } else { + svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); + multiplex = 1; + } } else { svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);