From patchwork Tue Jan 15 13:32:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Afzal Mohammed X-Patchwork-Id: 1978131 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id A681BDF264 for ; Tue, 15 Jan 2013 13:32:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757022Ab3AONbT (ORCPT ); Tue, 15 Jan 2013 08:31:19 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:58878 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756624Ab3AONbQ (ORCPT ); Tue, 15 Jan 2013 08:31:16 -0500 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r0FDVChA009061; Tue, 15 Jan 2013 07:31:13 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r0FDVCok004964; Tue, 15 Jan 2013 19:01:12 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Tue, 15 Jan 2013 19:01:11 +0530 Received: from ucmsshproxy.india.ext.ti.com (dbdp20.itg.ti.com [172.24.170.38]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with SMTP id r0FDVBwu003038; Tue, 15 Jan 2013 19:01:11 +0530 Received: from symphony.india.ext.ti.com (unknown [192.168.247.13]) by ucmsshproxy.india.ext.ti.com (Postfix) with ESMTP id 955C6158002; Tue, 15 Jan 2013 19:01:11 +0530 (IST) Received: from ubuntu-psp-linux.india.ext.ti.com (ubuntu-psp-linux [192.168.247.46]) by symphony.india.ext.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r0FDVBR02765; Tue, 15 Jan 2013 19:01:11 +0530 (IST) From: Afzal Mohammed To: Florian Tobias Schandinat , Tomi Valkeinen , Sekhar Nori , , , Subject: [PATCH v3 07/10] video: da8xx-fb: pix clk and clk div handling cleanup Date: Tue, 15 Jan 2013 19:02:15 +0530 Message-ID: <7fdf3e7770f0a7fec3efc71c87db88ebe12467ac.1358250489.git.afzal@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Use the new modedb field to store pix clk. Reorganize existing clock divider functions with names now corresponding to what they do, add common function prefix. Fix existing panel modedb pixclock to be in ps instead of Hz. This needed a change in the way clock divider is calculated. As modedb pixclock information is now in ps, override on "var" pixclock over modedb to var conversion is removed. Signed-off-by: Afzal Mohammed --- drivers/video/da8xx-fb.c | 48 +++++++++++++++++----------------------------- 1 file changed, 18 insertions(+), 30 deletions(-) diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index f1d88ac..7f08644 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -160,7 +160,6 @@ struct da8xx_fb_par { struct clk *lcdc_clk; int irq; unsigned int palette_sz; - unsigned int pxl_clk; int blank; wait_queue_head_t vsync_wait; int vsync_flag; @@ -201,7 +200,7 @@ static struct fb_videomode known_lcd_panels[] = { .name = "Sharp_LCD035Q3DG01", .xres = 320, .yres = 240, - .pixclock = 4608000, + .pixclock = 217014, .left_margin = 6, .right_margin = 8, .upper_margin = 2, @@ -216,7 +215,7 @@ static struct fb_videomode known_lcd_panels[] = { .name = "Sharp_LK043T1DG01", .xres = 480, .yres = 272, - .pixclock = 7833600, + .pixclock = 127655, .left_margin = 2, .right_margin = 2, .upper_margin = 2, @@ -231,7 +230,7 @@ static struct fb_videomode known_lcd_panels[] = { .name = "SP10Q010", .xres = 320, .yres = 240, - .pixclock = 7833600, + .pixclock = 127655, .left_margin = 10, .right_margin = 10, .upper_margin = 10, @@ -680,13 +679,14 @@ static void da8xx_fb_lcd_reset(void) } } -static void lcd_calc_clk_divider(struct da8xx_fb_par *par) +static inline unsigned da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, + unsigned pixclock) { - unsigned int lcd_clk, div; - - lcd_clk = clk_get_rate(par->lcdc_clk); - div = lcd_clk / par->pxl_clk; + return par->lcd_fck_rate / (PICOS2KHZ(pixclock) * 1000); +} +static inline void da8xx_fb_config_clk_divider(unsigned div) +{ /* Configure the LCD clock divisor. */ lcdc_write(LCD_CLK_DIVISOR(div) | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); @@ -694,7 +694,14 @@ static void lcd_calc_clk_divider(struct da8xx_fb_par *par) if (lcd_revision == LCD_VERSION_2) lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); +} + +static inline void da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, + struct fb_videomode *mode) +{ + unsigned div = da8xx_fb_calc_clk_divider(par, mode->pixclock); + da8xx_fb_config_clk_divider(div); } static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, @@ -705,8 +712,7 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, da8xx_fb_lcd_reset(); - /* Calculate the divider */ - lcd_calc_clk_divider(par); + da8xx_fb_calc_config_clk_divider(par, panel); if (panel->sync & FB_SYNC_CLK_INVERT) lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | @@ -969,7 +975,7 @@ static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); lcd_disable_raster(true); - lcd_calc_clk_divider(par); + da8xx_fb_calc_config_clk_divider(par, &par->mode); if (par->blank == FB_BLANK_UNBLANK) lcd_enable_raster(); } @@ -1195,22 +1201,6 @@ static struct fb_ops da8xx_fb_ops = { .fb_blank = cfb_blank, }; -/* Calculate and return pixel clock period in pico seconds */ -static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par) -{ - unsigned int lcd_clk, div; - unsigned int configured_pix_clk; - unsigned long long pix_clk_period_picosec = 1000000000000ULL; - - lcd_clk = clk_get_rate(par->lcdc_clk); - div = lcd_clk / par->pxl_clk; - configured_pix_clk = (lcd_clk / div); - - do_div(pix_clk_period_picosec, configured_pix_clk); - - return pix_clk_period_picosec; -} - static int fb_probe(struct platform_device *device) { struct da8xx_lcdc_platform_data *fb_pdata = @@ -1303,7 +1293,6 @@ static int fb_probe(struct platform_device *device) par = da8xx_fb_info->par; par->lcdc_clk = fb_clk; par->lcd_fck_rate = clk_get_rate(fb_clk); - par->pxl_clk = lcdc_info->pixclock; if (fb_pdata->panel_power_ctrl) { par->panel_power_ctrl = fb_pdata->panel_power_ctrl; par->panel_power_ctrl(1); @@ -1368,7 +1357,6 @@ static int fb_probe(struct platform_device *device) da8xx_fb_var.grayscale = lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; - da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par); /* Initialize fbinfo */ da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;