From patchwork Thu May 30 09:41:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 2635421 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 3D34BDFE82 for ; Thu, 30 May 2013 09:41:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S968060Ab3E3JlX (ORCPT ); Thu, 30 May 2013 05:41:23 -0400 Received: from mail-wg0-f47.google.com ([74.125.82.47]:46801 "EHLO mail-wg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S968065Ab3E3JlM (ORCPT ); Thu, 30 May 2013 05:41:12 -0400 Received: by mail-wg0-f47.google.com with SMTP id e11so24848wgh.26 for ; Thu, 30 May 2013 02:41:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:in-reply-to:references:content-type:x-gm-message-state; bh=GdGht+mBvPsYvo5o1vuzGONkv/jQ5ynLwOKuOGXiNFg=; b=X9zp/KAUCN3sQhXxxJcMS74kMApEobmp2GE1tbiaXJsyrbCWJoGtVJiC+0KMgnBgiA nTjXwXMesE2sPVh3mZ6++j/0s+e6VNEkB/Z50Ftin/yYRiN15TmLD9ibQBp8hXutGjSF 9qHajBNvAe81zuijpJ4c1m9uSEpAoJoefu/lHS2gzSwM47RAC3Jd0mjhRzl/Q0SExd0X 6v8Rta/tB30Q6cY0P5ZmE5EJyiWcx4knI6A9wIon5yyd0fCEq/irJYInvNsvrKZrUwQe O0g2kH35OSs4VkjxDw0hEf+hEsgS7QD3nSDs2T1VC6u6dEUT+YgIUem3Zf9a2/AdlEc7 2C6Q== X-Received: by 10.180.99.232 with SMTP id et8mr17622751wib.17.1369906871238; Thu, 30 May 2013 02:41:11 -0700 (PDT) Received: from localhost (nat-63.starnet.cz. [178.255.168.63]) by mx.google.com with ESMTPSA id b11sm36635614wiv.10.2013.05.30.02.41.09 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 30 May 2013 02:41:10 -0700 (PDT) From: Michal Simek To: linux-kernel@vger.kernel.org Cc: Michal Simek , Michal Simek , Florian Tobias Schandinat , linux-fbdev@vger.kernel.org Subject: [PATCH v2 2/3] video: xilinxfb: Do not use out_be32 IO function Date: Thu, 30 May 2013 11:41:01 +0200 Message-Id: X-Mailer: git-send-email 1.8.2.3 In-Reply-To: <27e53d5633766ab0dc1ac492023d5a0d0199e3aa.1369906849.git.michal.simek@xilinx.com> References: <27e53d5633766ab0dc1ac492023d5a0d0199e3aa.1369906849.git.michal.simek@xilinx.com> In-Reply-To: <27e53d5633766ab0dc1ac492023d5a0d0199e3aa.1369906849.git.michal.simek@xilinx.com> References: <27e53d5633766ab0dc1ac492023d5a0d0199e3aa.1369906849.git.michal.simek@xilinx.com> X-Gm-Message-State: ALoCoQmC8pMKTy2lxkrSc8P3UzZSM/WMovzOqAsk5hhFXUzT5gXeIBnptPsBnBsFaog8rGOraVkE Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org out_be32 IO function is not supported by ARM. It is only available for PPC and Microblaze. Remove all out_be32 references and start to use __raw_writel function. Signed-off-by: Michal Simek --- Changes in v2: None drivers/video/xilinxfb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- 1.8.2.3 diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c index aecd15d..000185a 100644 --- a/drivers/video/xilinxfb.c +++ b/drivers/video/xilinxfb.c @@ -57,7 +57,7 @@ * In case of direct PLB access the second control register will be at * an offset of 4 as compared to the DCR access where the offset is 1 * i.e. REG_CTRL. So this is taken care in the function - * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of + * xilinx_fb_out32 where it left shifts the offset 2 times in case of * direct PLB access. */ #define NUM_REGS 2 @@ -150,11 +150,11 @@ struct xilinxfb_drvdata { * To perform the read/write on the registers we need to check on * which bus its connected and call the appropriate write API. */ -static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset, +static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, u32 val) { if (drvdata->flags & PLB_ACCESS_FLAG) - out_be32(drvdata->regs + (offset << 2), val); + __raw_writel(val, drvdata->regs + (offset << 2)); #ifdef CONFIG_PPC_DCR else dcr_write(drvdata->dcr_host, offset, val); @@ -197,7 +197,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi) switch (blank_mode) { case FB_BLANK_UNBLANK: /* turn on panel */ - xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); + xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); break; case FB_BLANK_NORMAL: @@ -205,7 +205,7 @@ xilinx_fb_blank(int blank_mode, struct fb_info *fbi) case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_POWERDOWN: /* turn off panel */ - xilinx_fb_out_be32(drvdata, REG_CTRL, 0); + xilinx_fb_out32(drvdata, REG_CTRL, 0); default: break; @@ -280,13 +280,13 @@ static int xilinxfb_assign(struct device *dev, memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize); /* Tell the hardware where the frame buffer is */ - xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys); + xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); /* Turn on the display */ drvdata->reg_ctrl_default = REG_CTRL_ENABLE; if (pdata->rotate_screen) drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; - xilinx_fb_out_be32(drvdata, REG_CTRL, + xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); /* Fill struct fb_info */ @@ -345,7 +345,7 @@ err_cmap: iounmap(drvdata->fb_virt); /* Turn off the display */ - xilinx_fb_out_be32(drvdata, REG_CTRL, 0); + xilinx_fb_out32(drvdata, REG_CTRL, 0); err_fbmem: if (drvdata->flags & PLB_ACCESS_FLAG) @@ -381,7 +381,7 @@ static int xilinxfb_release(struct device *dev) iounmap(drvdata->fb_virt); /* Turn off the display */ - xilinx_fb_out_be32(drvdata, REG_CTRL, 0); + xilinx_fb_out32(drvdata, REG_CTRL, 0); /* Release the resources, as allocated based on interface */ if (drvdata->flags & PLB_ACCESS_FLAG) {