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Tue, 24 May 2022 02:51:03 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Received: from [10.140.6.60] (port=58200 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1ntR8u-0005Sf-CC; Tue, 24 May 2022 02:47:56 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , Subject: [PATCH 0/3]Adds status interface for zynqmp-fpga Date: Tue, 24 May 2022 15:17:42 +0530 Message-ID: <20220524094745.287002-1-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a8ea0c78-aad6-4c0a-ca2a-08da3d6af3e7 X-MS-TrafficTypeDiagnostic: MWHPR02MB2542:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 09:51:19.3447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8ea0c78-aad6-4c0a-ca2a-08da3d6af3e7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0030.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2542 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds status interface for zynqmp-fpga, It's a read only interface which allows the user to get the PL status. This patch series also update the below status values for fpga-manager. -Device Initialization error. -Device internal signal error. -All I/Os are placed in High-Z state. -Device start-up sequence error. -Firmware error. For more details refer the ug570. https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration Nava kishore Manne (3): fpga: mgr: Update the status for fpga-manager firmware: xilinx: Add pm api function for PL readback fpga: zynqmp-fpga: Adds status interface drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++ drivers/fpga/fpga-mgr.c | 13 +++++++ drivers/fpga/zynqmp-fpga.c | 52 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 14 ++++++++ include/linux/fpga/fpga-mgr.h | 6 ++++ 5 files changed, 118 insertions(+)