From patchwork Fri Dec 9 01:23:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 13069124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E9C8C4167B for ; Fri, 9 Dec 2022 01:25:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229737AbiLIBXc (ORCPT ); Thu, 8 Dec 2022 20:23:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229530AbiLIBXa (ORCPT ); Thu, 8 Dec 2022 20:23:30 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 352037E838; Thu, 8 Dec 2022 17:23:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670549009; x=1702085009; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=kU+kYZJk4GQdVd2wAkmEMaH9RmpyenBLTdAz4UYSb7E=; b=RJscMbU1UMTKlompmPQXeRdomdjgi9h51JRwtJluRTi7qjFuV98FsTPl 2CH+7KMWPgTWbSt1FsTA3UPhjCPlUwvTRbbrjeg8wFcDENs5zvymy6FOP zJbPiUi0AYE47Dauj34FsnTaWeUZV3s0qLk3xtQyCgML5eZflSw1vhqxh zmutcdh9QSin7XcIzNN9cN22D+uru9bRKfKkq8ahqAlvFRM/Uh6xBXPHX vx+aqtU/LImUHqBfRDGQw09EwiRQPDXiGSgruWFZoO+pnOOrEMSSEQwlb SzKdHCcmZ/Qo7g0MzySx6WxDqhddjf8rtR1OCwGU5D4ZxjSK/DXxfwD+L g==; X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="318504833" X-IronPort-AV: E=Sophos;i="5.96,228,1665471600"; d="scan'208";a="318504833" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 17:23:28 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="715852787" X-IronPort-AV: E=Sophos;i="5.96,228,1665471600"; d="scan'208";a="715852787" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.139]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 17:23:28 -0800 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com, marpagan@redhat.com Cc: Matthew Gerlach Subject: [PATCH v5 0/4] Enhance definition of DFH and use enhancements for UART driver Date: Thu, 8 Dec 2022 17:23:44 -0800 Message-Id: <20221209012348.2883424-1-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Matthew Gerlach This patchset enhances the definition of the Device Feature Header (DFH) used by the Device Feature List (DFL) bus and then uses the new enhancements in a UART driver. The enhancements to the DFH includes the introduction of parameter blocks. Like PCI capabilities, the DFH parameter blocks further describe the hardware to software. In the case of the UART, the parameter blocks provide information for the interrupt, clock frequency, and register layout. Duplication of code parsing of the parameter blocks in multiple DFL drivers is a concern. Using swnodes was considered to help minimize parsing code duplication, but their use did not help the problem. Furthermore the highly changeable nature of FPGAs employing the DFL bus makes the use of swnodes inappropriate. Patch 1 updates the DFL documentation to describe the added functionality to DFH. Patch 2 adds the definitions for DFHv1. Patch 3 adds basic support for DFHv1. It adds functionality to parse parameter blocks and adds the functionality to parse the explicit location of a feature's register set. Patch 4 adds a DFL UART driver that makes use of the new features of DFHv1. Basheer Ahmed Muddebihal (1): fpga: dfl: Add DFHv1 Register Definitions Matthew Gerlach (3): Documentation: fpga: dfl: Add documentation for DFHv1 fpga: dfl: add basic support for DFHv1 tty: serial: 8250: add DFL bus driver for Altera 16550. Documentation/fpga/dfl.rst | 103 +++++++++++++ drivers/fpga/dfl.c | 234 ++++++++++++++++++++++------- drivers/fpga/dfl.h | 37 +++++ drivers/tty/serial/8250/8250_dfl.c | 147 ++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 12 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 15 ++ 7 files changed, 498 insertions(+), 51 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_dfl.c