Message ID | 20240726063819.2274324-1-nava.kishore.manne@amd.com (mailing list archive) |
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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF0000468B.mail.protection.outlook.com (10.167.243.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7784.11 via Frontend Transport; Fri, 26 Jul 2024 06:38:28 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 26 Jul 2024 01:38:21 -0500 From: Nava kishore Manne <nava.kishore.manne@amd.com> To: <git@amd.com>, <mdf@kernel.org>, <hao.wu@intel.com>, <yilun.xu@intel.com>, <trix@redhat.com>, <robh@kernel.org>, <saravanak@google.com>, <linux-fpga@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [RFC 0/1]Add user space interaction for FPGA programming Date: Fri, 26 Jul 2024 12:08:18 +0530 Message-ID: <20240726063819.2274324-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: <linux-fpga.vger.kernel.org> List-Subscribe: <mailto:linux-fpga+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-fpga+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468B:EE_|DM4PR12MB6279:EE_ X-MS-Office365-Filtering-Correlation-Id: 217018b3-bbfe-4e83-0d44-08dcad3d8f26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|921020; 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Add user space interaction for FPGA programming
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