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[v2,3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

Message ID 1488126948-9466-4-git-send-email-matthew.gerlach@linux.intel.com (mailing list archive)
State Superseded, archived
Headers show

Commit Message

Matthew Gerlach Feb. 26, 2017, 4:35 p.m. UTC 
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Device Tree bindings for Altera Partial Reconfiguration IP.

v2: s/Reconfiguraion/Reconfiguration/
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Patch

====================

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
new file mode 100644
index 0000000..ada821f
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
@@ -0,0 +1,12 @@ 
+Altera Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,pr-ip"
+- reg        : base address and size for memory mapped io.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ff20c000 {
+		compatible = "altr,pr-ip";
+		reg = <0xff20c000 0x10>;
+	};